To install StudyMoose App tap and then “Add to Home Screen”
Save to my list
Remove from my list
After outputting the number sequence once, the circuit will not generate any other outputs until the next Start "1" signal. Results To design the required circuit, VHDL programming approach has been implemented first. The circuit has been programmed using three different files for counter, combinational comparator and shift register. Following are the corresponding files with the short explanation of the code. Code for the 4-bit counter is shown in Fig. 5. It can be seen that when the Start becomes "1", the counter begins to count, however it continues to count only in that case if Start goes back to "0" on the next clock cycle.
At the same time the tmp_enable_1 signal (output Enable_1) becomes "1" for the next 8 cycles to enable the shift register to input data.
On completion of 8 cycles, Enable_1 returns to "0" disconnecting shift register from the input, and Enable_2 becomes "1" enabling the comparator to input two 4-bit numbers from the shift register. Code for the shift register is shown in Fig. 6. When shift register is enabled, it takes and propagates the input bits for eight clock cycles.
Verified writer
Proficient in: Computers
5 (876)
“ Have been using her for a while and please believe when I tell you, she never fail. Thanks Writer Lyla you are indeed awesome ”
After eight clock events, inputting stops, and received numbers are ready to be read by comparator.
Comparator acts as following. Upon receiving an enable signal, comparator compares two 4-bit numbers and outputs the Data Ready signal. On the next clock cycle, the LSB of the largest number (or number A if they are equal) is outputted through Data Out line. Next the 4-bit number is rotated inside itself so that the 2nd LSB is the array position "0".
On the next clock cycle it is outputted through the same port. And so on until all 4 numbers are out. The resulting top level VHDL code is shown below.
Having compiled and debugged the code, it has been simulated with the test bench waveform. The following input data have been selected: "00100111". It should be noted that the LSB is being inputted first. Having selected the right timing for the Reset and Start signal, a resulting output waveform has been produced to confirm the correct operation of the circuit.
The sequence of the test is the following:
Having implemented the circuit in the VHDL code, it will be looked at as an electronic entity.
First of all, the shift registers will be implemented using flip-flops, and then a 4-bit counter will be designed as well. The comparator will not be implemented in the current report, however it should be mentioned that it is a combinational device.
Shift Register consists of 8 D flip-flops. As soon as Enable_1 signal of the counter becomes '1', tri-state buffer opens, and input bits are propagated along the flip-flops for 8 clock cycles. After 8 clock cycles, all bits are ready to be taken by the comparator. 4-bit counter: 4-bit counter controls two other components, comparator and shift register, by means of two outputs, Enable_1 and Enable_2. When Enable_1 is 'high', tri-state buffer of the shift register opens to allow the data in. When Enable_2 is 'high', comparator is ready to compare the two numbers.
The counter itself is enabled by the Start 'high' signal for one clock cycle. After that the StAB+AD+AC The resulting Boolean expressions were used to build a circuit of logic gates of JK flip-flops.
After running a circuit with the Reset and Start input from the word generator, the results could be confirmed with the logic analyser: It can be seen that after Reset signal and then Start, Output 1 becomes 'high' for 8 clock cycles to enable shift register input, then Output 2 becomes 'high' to enable comparator. When counter reaches'1111' state, both outputs return to 'low'. As it was mentioned above, the comparator will not be schematically designed for the purpose of this report. Its functionality consists of inputting two 4-bit numbers on the enable signal from the counter, and then comparing them.
Once compared, the Ready signal becomes 'high' for one clock cycle, and then the largest number is serially comes out on the Data Out port. Once all four bits are out and buffered, outputting stops. Conclusion A sequential synchronous circuit was designed using VHDL programming method, and then expanded based on the knowledge of the electronic components. Program code has been debugged and simulated. The resulting waveforms confirmed the expected operation. In my personal experience, VHDL programming method evolved into working design much easier as compared to the time and effort it would take using just schematic approach.
Once the problem is specified in the pseudo language, it can be rather straightforward put into the VHDL code. However not everyone can comprehend programming languages. Although majority of designers will benefit from the usage of VHDL programming, some may encounter certain difficulties and may have to use less advanced techniques. Mini-project Show preview only The above preview is unformatted text This student written piece of work is one of many that can be found in our University Degree Physics section.
VHDL. Is it easy, or not. (2020, Jun 02). Retrieved from https://studymoose.com/vhdl-easy-not-step-forward-12082-new-essay
👋 Hi! I’m your smart assistant Amy!
Don’t know where to start? Type your requirements and I’ll connect you to an academic expert within 3 minutes.
get help with your assignment
