 

 

Carry Skip Adder using Reversible Logic PERES and FREDKIN gateS.Srikanth1, S. Aarthimeena2, A.Abarnaa2, K.Brindha21 – Assistant Professor, Department of ECE, SNS College of Technology, Coimbatore – 352 – B.E Student, Department of ECE, SNS College of Technology, Coimbatore ” 35 ABSTRACT In digital IC designing energy dissipation has become a crucial factor which engineers would consider before they begin the design. However irreversible logic computing is one of the most significant factors of energy dissipation due to bit loss. Therefore designing IC by reversible logic has become one of the directions in low power dissipating circuit design, since it has the ability to recover from bit loss in irreversible logic through unique mapping between input and output vector.
In this paper, we proposed a 16bit Carry Skip Adder which is an optimization of Ripple Carry Adder designed by reversible logic gates. The proposed gate reduces the hardware complexity with minimum constant input and garbage output. KEYWORDS: Reversible logic gates, Adder, Conventional Carry Skip Adder, Reversible logic Carry Skip Adder, Xilinx outputs.
I.INTRODUCTION:Irreversible logic circuits dissipates heat in the amount of KT ln2 Joule for every bit of information lost which is based on Landauer’s principle, where K “Boltzmann constant and T is the temperature of the heat sink in Kelvin and ln2 is the natural logarithm of 2.Thus we moved to reversible logic gates which do not erase information so dissipate zero power. It is based on the concept of Bijective Boolean function where the output vector is a permutation of all the input combinations. Therefore input vector states can be always uniquely retrieved from the output. In order to make the equal size of the input and output count we add additional inputs called as ancilla input or control input while extra output are called as garbage output. II.REVERSIBLE LOGIC GATES:There exists many reversible gates among them 2*2 feyman gate ,3*3 fredkin gate ,3*3 toffoli gate and 3*3 peres gate is the most referred. The quantum cost of a reversible gate depends on any particular realization of quantum logic. Generally, the total quantum cost of a circuit is calculated by summing the cost of all individual primitive logic gates used. The cost of toffoli gate and fredkin gate and is 5. The quantum cost of 3*3 peres gate is 4 and it is the best reversible logic gate used to design a full adder with minimum quantum cost. Fig.1. 2*2 Feynman Gate Fig.2. 3*3 Fredkin Gate Fig.3. 3*3 Peres Gate Fig.4. 3*3 Tofolli Gate III.ADDER:In digital circuits an adder is used to perform addition of two numbers. Adders in the arithmetic logic units are used to calculate addresses, table indices, increment and decrement operators, and similar operations. Most of adder operates on binary number which adds N bit numbers. To add Nbit numbers it is possible to create logical circuit using multiple full adders. In ripple carry adder (RCA) the carry out of each full adder is given as input to the succeeding next most full adder. Since each carry bit “ripples” to the next full adder it is called ripple carry adder. Ripplecarry adder has a simple layout which promotes fast design time. However, the ripplecarry adder is relatively slow, since succeeding full adder must wait for the carry bit to be calculated from the previous full adder. In order to overcome the above disadvantage, carry skip adder (CSA) has been implemented which has shortest time delay. In this paper we proposed a 16 bit carry skip adder using reversible logic gate that is both time efficient and decline the amount of power dissipating in irreversible logic gate. . IV. CONVENTIONAL CARRY SKIP ADDER: Fig.5. 16 bit Conventional Carry Skip Adder Traditional carry skip adder is an optimization of ripple carry adder with minimum time delay by using carry skip logic. The 16 bit CSA is constructed by 4 parts of 4 bit CSA connected serially. Each 4 bit CSA consists of sum logic and skip logic. RCA is for sum logic which is given with 8bit of inputs. In 1st 4bit CSA input is (a0a3, b0b3) and an input carry c0. The sum out and carry outs are (s0s3), (c0c3). For considering 16 bit it will have 32 bit of inputs (a0a15, b0b15) and the output carry of each 4bit CSA is given as input to the next 4bit CSA. Therefore, the sum out and carry outs are (s0s15), (c0c16). Skip logic consists of a comparison block and a MUX. In comparison block the input signal undergoes EXOR operation and then it is given as input to an AND gate. For example, in the first 4bit CSA, it is operated as SL0= (a0^b0) & (a1^b1) & (a2^b2) & (a3&b3). Here (ai^bi) =Pi, and this output of AND gate is given to a 2:1 mux as selection line. If 1 is selected the input carry is propagated as output of that 4bit CSA or if 0 is selected the carry out of that block is generated as output. That is, if input (ai=bi) the propagated signal pi will be 0 hence output of AND gate will also be 0 then mux will take 0 as select line. We can say that carry must be generated over that block. Otherwise, if ai!=bi the propagated signal will be 1 hence the output of AND gate will also be 1 then mux will take 1 as select line . We can say that the carry skips over that block.For example let us consider,A0 1 10 0 1 1 0 0 1 1 0 0 1 1 0 B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Block 0 Block 1 Block 2 Block 3Here ai and bi are not completely reversed hence the propagated signal will be 0 ,then mux will take 0 as select line and the generated carry will be the output .A 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Block 0 Block 1 Block 2 Block 3Here ai and bi are completely reverse hence the propagated signal will be 1, then mux will take 1 as select line and the input carry will be selected as output. The carryin of this block would simply be propagated to the next block without computing. This carry skip mechanism shortens the length of delay of computing the carry of this block. V.PROPOSED REVERSIBLE LOGIC CARRY SKIP ADDER:Using reversible logic to redesign a 16 bit CSA each block needs to be transformed into a reversible logic block by using reversible logic gates. In this paper we redesigned, ripple carry adder block using 4 PERES full adder gate and comparison block AND gate with 3 PERES gate and then 2:1 mux with 1 FREDKIN gate.Reversible logic implementation of half adder circuitHalf adder is the fundamental building block in many computational units here we have designed half adder using peres gate by assigning input c as constant input. Fig.6. Peres Half Adder Gate Fig.7. Peres Half Adder Gate logic diagramReversible Logic Implementation of Full Adder Circuit:The outputs of full adder circuit are given by sum and carry equations_Sum=a^b^cin Carry= (a&b)(b&cin)(cin&a)In this paper we proposed a quantum cost efficient reversible peres gate full adder circuit that is realized by cascading two 3*3 Peres gates only. The quantum realization cost of this gate is 8 since it includes two 3*3 Peres gates. When the fourth input of gate is set to zero (D=0) the gate can work singly as a reversible full adder. This logic realization of full adder circuit includes two garbage outputs, one constant input and requires only one clock cycle. In terms of gate count, garbage outputs and constant input this implementation of reversible full adder circuit is also efficient than the existing counter parts. For ripple carry adder block this Peres gate full adder is taken Fig.8.Peres Full Adder using two Peres half adder gate Fig.9. Peres Full Adder Gate Fig.10. Peres Full Adder Gate logic diagramREVERSIBLE LOGIC COMPARISON BLOCK:AND GATE:In comparison block the AND gate is redesigned with 3 Peres gate assigning c=0 as control input and P and Q as garbage output. For example considering 4bitCSA, the propagated signal p0 and p1 from PFAG1 and PFAG2 is given to 1st Peres gate which do the AND operation and gives p01= (a0^b0) & (a1^b1). Propagated signal p2 and p3 from PFAG3 and PFAG4 is given to 2nd Peres gate which do the AND operation and gives output p02= (a2^b2) & (a3&b3). This p01 and p02 is given to another Peres gate which do the AND operation and gives p03= (p01&p02). This p03 output is given as selection line to the mux. Fig.11. Peres AND GateMUX:The 2:1 mux is redesigned with reversible 3*3 FREDKIN gate of quantum cost 5. The input carry and generated carry are given as input. Propagated signal from Peres AND gate is taken as selection line. The output from this mux is given as input carry to the next 4 bit CSA and the remaining two outputs are garbage outputs. Considering, first 4bit CSA inputs are c0, ca3 and the propagated signalP03 will be selection line. The output expression will be c01= ((P03&ca3) ^ (P03&c0)). The carry out c04 from the last 4bit CSA is the final output. Fig.12. Fredkin Gate MUX BLOCK DIAGRAM OF 16 BIT REVERSIBLE CSA: Fig.13. 16 bit Reversible Carry Skip Adder VI.EXPERIMENTAL RESULTS:We had executed the design in XILINX ISE DESIGN using Verilog code. In output waveform 1, we had given input carry c0=0with 32 bit of input. A 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Block 0 Block 1 Block 2 Block 3Since the inputs are completely reversed propagate signal will be 1 hence input carry is selected and propagated asOutputs skipping all the carry generated in ripple carry adders.In output waveform 2, we had given input carry c0=0 with 32 bit of inputs as,A0 1 10 0 1 1 0 0 1 1 0 0 1 1 0 B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The inputs are not completely reversed. Therefore, the propagated signal will be 0 hence the output carry generated by ripple carry adder is selected as output.
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Carry Skip Adder using Reversible Logic PERES and FREDKIN gateSSrikanth1 S Aarthimeena2. (2019, Aug 20). Retrieved from https://studymoose.com/carryskipadderusingreversiblelogicperesandfredkingatessrikanth1saarthimeena2essay