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An efficient technique for multiplying two binary numbers using limited power and time is presented in this paper. The work mainly focuses on the speed of the multiplication operation of multipliers by reducing the number of bits to be multiplied. The framework of the proposed algorithm is taken from Mathematical algorithms given in Vedas and is further optimized by the use of some general arithmetic operations such as expansion and bit-shifting. The proposed algorithm was modeled using Verilog, a hardware description language.
It was found that under a given 3.3 V supply voltage, the designed 4-bit multiplier dissipates a power of 47.35 mW. The propagation time of the proposed architecture was found to be 6.63 ns.
Digital multipliers are essential components in digital signal processors (DSPs), and the speed of DSPs largely depends on the speed of their multipliers. This paper introduces a new multiplication algorithm that reduces the need for large multipliers, thereby significantly reducing propagation delays.
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The proposed algorithm is based on the Nikhilam Sutra of Vedic mathematics and is further optimized to take full advantage of bit reduction in multiplication. Traditional multiplication algorithms, such as array multiplication and Booth multiplication, are commonly used in digital hardware but can be time-consuming.
This paper aims to address these issues by applying Vedic mathematics principles to develop a more efficient multiplication algorithm, particularly suitable for large numbers. The proposed algorithm is shown to be computationally efficient, reducing a 4x4-bit multiplication to a single 2x2-bit multiplication operation.
Two commonly used multiplication algorithms in digital hardware are the array multiplication algorithm and the Booth multiplication algorithm.
The array multiplication algorithm calculates partial products independently in parallel, reducing computation time. However, it still incurs delay due to signal propagation through gates.
Booth multiplication, on the other hand, requires large arrays for high-speed multiplication and exponential operations, leading to substantial propagation delays. In this context, the proposed algorithm offers a novel approach to multiplication by reducing large numbers to smaller ones, thus minimizing propagation delays.
Research in digital multipliers is an active area, with several multiplication algorithms reported in the literature [6]-[9]. This paper presents a unique approach to multiplication by utilizing Vedic mathematics principles.
The rest of the paper is structured as follows: Section II provides a brief overview of Vedic mathematics. Section III introduces the Vedic multiplication Sutras and describes the proposed algorithm. Finally, Section IV presents concluding remarks.
Vedic mathematics is an ancient Indian system rediscovered in the early twentieth century. It incorporates mathematical formulae and principles found in ancient Indian scriptures (Vedas). Vedic mathematics simplifies and optimizes various branches of mathematics, including arithmetic, algebra, and geometry.
Vedic mathematics is based on 16 Sutras, or aphorisms, that deal with different mathematical concepts. These Sutras enable the simplification and optimization of conventional mathematical calculations. They are derived from ancient Vedic texts and offer effective algorithms for various engineering fields, including computing and digital signal processing.
The proposed multiplication algorithm combines the Urdhva tiryakbhyam Sutra with the principles of binary arithmetic. The algorithm reduces the multiplication of large numbers to that of smaller numbers, effectively minimizing propagation delays.
The Urdhva tiryakbhyam Sutra is first adapted to the binary number system to develop a digital multiplier architecture. This architecture is similar to the popular array multiplier architecture.
Nikhilam Sutra is then introduced as a more efficient multiplication algorithm for large numbers. It reduces the multiplication of two large numbers to that of two smaller ones, taking full advantage of bit-reduction in multiplication.
To illustrate the efficiency of the proposed algorithm, we consider a 4x4-bit multiplication reduced to a single 2x2-bit multiplication operation. This showcases the fundamental principles of the algorithm.
| 5 | 4 | 9 | 8 | |
| × | 6 | |||
| Gunitasamuchyah | 0 | 1 | 2 | |
| 1 | 0 | |||
| 0 | 8 | |||
| 1 | 1 | 2 | ||
| 5 | 2 | |||
| 0 | 0 | |||
| 5 | 4 | |||
| 2 | 1 | |||
| 0 | 6 | |||
| 2 | 2 | 1 | ||
| 1 | 1 | 2 | ||
| 8 | 6 | |||
| 2 | 2 | 3 | ||
| 7 | 4 | |||
| 0 | 0 | 1 | ||
| 9 | 8 | |||
| 3 | 3 | 4 | ||
| 6 | 2 |
5498 X 2314 = 12722372
Carry: 1 2 7 2 2 3 7 2
In conclusion, the Vedas Multiplier Algorithm offers a novel approach to multiplication in VLSI arithmetic. By combining principles from Vedic mathematics and binary arithmetic, the algorithm minimizes propagation delays and reduces the need for large multipliers. This research has the potential to significantly improve the speed and efficiency of digital signal processors and other computation systems.
The application of Vedic mathematics principles to digital arithmetic is a promising area for further exploration, with potential applications in various engineering fields. The 16 Vedic Sutras provide a rich source of algorithms that can simplify and optimize complex mathematical calculations.
Future research can focus on implementing the Vedas Multiplier Algorithm in practical VLSI systems and evaluating its performance in real-world applications. This work lays the foundation for more efficient and faster multiplication operations in digital hardware.
Vedas Multiplier Algorithm in VLSI Arithmetic. (2024, Jan 24). Retrieved from https://studymoose.com/document/vedas-multiplier-algorithm-in-vlsi-arithmetic
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