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In Digital signal processing, filters are used in all devices. Filters are used to extract a useful part from the input Signal and there queried part of the signal is reached to the receiver. In this Paper, FIR filter has been designed using a Vedic multiplier and SQRT-CSLA (carry select adder). Combination of both Vedic multiplier and SQRT-CSLA (carry select adder) makes the FIR filter faster. For reducing the area of CSLA, it can be implemented by using a single RCA and an add one circuit instead of using dual RCA.
The design of SQRT-CSLA by using RCA and BEC. The RTL synthesis using Xilinx 14.7 and simulations going to be done by using modelsim. The proposed design would be efficient in terms Of Speed and complexity.
In recent years of technology development in Signal processing application, an FIR (Finite impulse response) filter design will have a highly compactable with high performance and low power in all digital signal processing application, such as audio, signal processing, software defined radio and many more.
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Digital signal processing is an important part of electronic devices whereas a signal is an information, which we want to transfer from sender to receiver through a medium called channel. FIR Filter plays an important role in designing an efficient digital signal processing system. An FIR filter has not required a feedback based inputs, which means, this filter is not computed any rounding errors in summing and multiplication. An FIR Filter is inherently stable to produce output values and it can be no maximum value impulse response Nth order times[3].
For the efficient understanding of FIR filter a) Distributed Arithmetic (DA) and b) Multiple Constant Multiplication (MCM) techniques are used.
In DA-design, to decrease the computation LUT's are used for the storage of pre-computed results. In MCM design, the additions required for computation get reduce and it is more effective because it uses common sub-expression sharing [8]. In the FIR Filter, the design will take a large area and take the stringent order to meet frequency range with high performance. In the FIR Filter architecture will have to MCM (Multiple constant multiplications), adders and delayed element, here the MCM multiplier will not identify the method of signed and unsigned operation, this multiplier will configure either signed or unsigned. In the FIR filter Nth, an order of the filter increases, efficiency of FIR will increase, then the number of addition and multiplication required to get increased. The drawback of FIR filter design is a large area and more power consumption, because it uses impulse response of Nth order based circuit, its contain multiplier, adder and delayed element [5].
FIR filter is a type of digital filter, which is used for linear characteristics applications. Various types of techniques have been proposed for the designing of the FIR filter. Designing of FIR filter by using Multiplier and adder. The selected multiplier and adder should be faster. Normal FIR Filter provides high die size (area) and high power utilization [9]. To overcome this problem, the reduced Vedic multiplier is composed by urdhva-tiryagbhyam technique and an adder is used for addition purpose. The adder is one of the key hardware blocks in Arithmetic and logic unit (ALU) and digital signal processing (DSP) systems [2]. The DSP applications where an adder plays a significant role include difficulty, digital filtering like in Discrete Fourier transform (DFT) and Fast Fourier Transform (FFT), digital communications and spectral analysis. The performance depends on the power consumed while addition operation.
Vedic Multiplier is based on ancient Indian Vedic Mathematics. Vedic mathematics contains 16 Sutras (formulae) mainly for the multiplication process. They all deal with various branches of mathematics like arithmetic, algebra, geometry, etc. Among all of the 16 Sutras, Urdhva-Tiryakbhyam is the most used method. Vertical and horizontal multiplication is carried out to reduce the partial product generation stages. The formula enables the parallel generation of partial products and eliminates unwanted multiplication steps. A reconfigurableVedic multiplier has been selected which is a high-speed multiplier [4]. Vedic Multiplier is an efficient one compared to other multipliers like Array Multiplier, Booth Multiplier, etc. based on area, speed.
Vedic Multiplier has one advantage that is the number of bits increases, area, and gate delay increases very slowly as compared to other multipliers. Finally, this reduced Vedic multiplier unit is applied into the transposed form block FIR filter to achieve the low area, delay, and low power. FIR filter also contains adder in the circuit to add the partial products during the multiplication process. An adder in the data path is required, which consumes less area and power with analogous speed. In Section-III presents a logic for Vedic Algorithm based multiplication operation. Section-IV deals with the Comparison of Different types of multipliers. Section-V Survey of CSLA Adders. Section–VI deals with the Proposed Structure of Vedic Multiplier FIR filter design. Section – VII deals with the Synthesis results and comparison of different Multipliers using for FIR filter followed by Conclusion and References.
2011 IEEE, B. Ramkumar, Harish M Kittur, discuss the fast arithmetic operation via to different adders. Carry select adder is one among of all the design of fast arithmetic functions. In the structural design of carry select adder to considerably have a large area to be reduced, and also power use. The proposed design of SQRT -CSLA will modify 8-, 16-, 32- and 64bit SQRT-CSLA design with compare to the regular Carry Select adder, it will show high performance in the area, power, and delay, this design of SQRTBEC based CSLA will reduce the area, power and delay [1].
2015 IEEE, PramodKumarMeher, BasantKumarMohanty discussed about the FIR Filter design in Fixed and Reconfigurable method of application, this FIR filters are hold up to natural pipelined multiplication, such as MCM (Multiplier constant multiplication) technique it will save the hardware area,size and power consumption. In this proposed work of this paper will realization of flow complexity in area of design and less energy per sample, and in this design using coefficient from the h(x), to reduce the impulse noise, with Nth order structure [3].
2007 IEEE, ShamimAkhter, In this paper, a new method of digit multiplication is presented. The design is based on Vedic method of multiplication. In this the vedic multiplier is designed for the 4-bit, 8-bit, 16-bit and 32-bit bit by using full adders and half adders. By this it gives us method for hierarchical multiplier design. Therefore, the design complexity gets reduced for inputs of large no of bits and modularity gets improved [2].
2017 SPIN(IEEE), ShamimAkhter, VikasSaini, Jasmine Saini , In this a relative analysis of Vedic multiplier using various digital adders has been done. The parameters compared were delay, area and power (dynamic and leakage) using digital standard cell library. The different adders like RCA, CSA, BEC, SQRT-CSA etc. are used in the multiplier. So depending upon the necessities, we can choose the adder consequently. The similar analysis can also be performed on further various adders [4].
2016 IEEE(SPIN), Deepika, NidhiGoel,A FIR filter has been designed by using Reconfigurable Booth multiplier. Reconfigurable multiplier is working on the concept of state machine. Proposed FIR filter has been designed by using behavioral modeling. Synthesis of proposed work has been done successfully. Proposed MAC unit can work for n number of bits. For this paper synthesis has been done for 16 bit. MAC unit is high speed unit which makes FIR filter faster [5].
2014 IEEE,B BasantKumarMohanty, SujitKumar Patel,,Compare to the regular Carry Select adder,it will show high performance in the parameters like area, power and delay, So the CSLA adder is designed using different architecture such as CBL based CSLA, BEC based CSLA and BEC based CSLA is designed to reduce the area, power and delay of the circuit in the multiplication process and choose the best performed among the above architectures based on the performance which can reduce the area, delay and power [6].
2015 IJRST,PriyaMeshram, MithileshMahendra and ParagJawarkar, SQRTCSLA are significantly reduced, proposed design show a decrease for 16-b, 32-bit sizes which indicates the success of the process and reduced delay ,power and area. The modified CSLA architecture is therefore, low area, low power, simple and efficient for VLSI hardware realization. The regular SQRTCSLA has the disadvantage of occupying more chip area. By reduceing the number of gates of this work offers the great advantage in the reduction of area. This paper proposes a scheme which reduces the area than the regular and modified SQRTCSLA. It would be interesting to test the design of the 64 and 128 bit SQRTCSLA [7].
For N x N multiplication, divide the multiplicand and multiplier into two parts, consisting of (N to N/2-1) bits and (N/2 to 1) bits. Among all the 16 sutras, the most and commonly used are only three for the multiplication purposes. Among the 16 methods (sutras), mostly general method is used for the multiplication process. The word Vedic is derived from the word Veda, which means storehouse of knowledge. The ‘Veda’ is a Sanskrit word and the word derived from the root word ‘Vid’. Meaning of this word ‘Vid’ is ‘know without limit’. Swami Bharati Krishna Tirtha (1884-1960), former JagadguruShankarachrayaMaharaj culled a set of 16 Sutras and 13 Sub Sutras from Atharva Veda. Here the sutra means aphorism & sub sutra mean corollary. Among the four Vedas, Vedic mathematics is one of them. Actually, it is the part of Sthapatya Veda, which is aupa Veda of Atharva Veda [10].
The Vedic mathematics is not a mathematical wonder but it is purely logical. All the formulas & sub formulas can be applied to geometry, trigonometry and differential integral calculus, applied mathematical problems. The advantage of Vedic mathematics is that, it reduces the complexity of conventional methods and turns into a simple method. All the formulas & sub formulas are based on natural principals like human brain. Therefore, this is a very interesting field in not only mathematics but in engineering also [11].
Urdhva-tiryakbhyamsutra:
The word “Urdhva-Tiryakbhyam” means vertical and crosswise multiplication. This multiplication formula is equally applicable to all cases of algorithm for N bit numbers. Usually this sutra is used for the multiplication of two numbers in decimal number system. The same concept can be applicable to binary number system . Advantage of using this type of multiplication method is that as the number of bits increases, delay and area increases very slowly as compared to other other multiplication method.
The number of operation that has to be performed is same as that in conventional multiplication method only thing is that delay.
In the above figure-1, 2-bit binary numbers x1x2 and y1y2 are considered. The result obtained is stored in each step. In the first step [x2,y2] is multiplied and the result obtained is stored and pervious carry is taken as 0. Similarly, in second step [x1,y2] and [x2,y1] are multiplied using a full adder and the sum is stored and carry is transferred to next step. Similarly, the process continues till we get the result.
In short, the ’Urdhva –Tiryakbhyam’ means ‘Vertically and crosswise’. The application of this sutra will ensure simpler means to solve typical multiplication. Vedic Multiplier architecture is quite different from the Conventional method of multiplication like add and shift. Therefore, it is time, power and area efficient [4]. In Fig 2, the digits on the both side of the line are multiplied and added with the carry of the previous step. It generates one of the bits of the result and a carry.
This carry is added to the next step multiplication result and hence the process goes on. If more than one line present in one-step, all the results are added to the carry of previous step. In each step, least significant bit (LSB) acts as the result bit and all other bits act as carry for the next step [2]. These partial products can be generated and added as per construction projected. The block diagram for 64x64 Multiplication based on Vedic technique as proposed in is shown in Fig 3. The first stage is four sets of 32x32 Multiplier, which is also based on Vedic technique.
As can be seen that adder is used in the intermediate addition, hence fast and area efficient design will enhance the overall performance of multiplication.
Example: 564 x 474 ( 3 digit numbers)
Array Multiplier
A Array (cluster) multiplier is a parallel multiplier. Which moves and includes at the same time. It comprises of a variety of adders. Exhibit multiplier utilizes moves and include's activity as in two fold multiplier however it includes the fractional items parallel. The every incomplete item is produced by the multiplicand and multiplier. It creates progressively halfway items, so it takes additional time, more region to get the last items.
Radix-4 Booth Multiplier
The Radix-4 Booth multiplier is a parallel multiplier. It is utilized to build the speed of the augmentation and it can decrease the halfway items .The Radix-4 Booth calculation is utilized to expand the speed of the multiplier and diminishes the territory of the multiplier. One of the arrangements of acknowledging rapid multipliers is to upgrade parallelism which diminishes the number of ensuing computation stages. The main idea is that as a substitute of adding and shifting of every column of multiplier term and multiplying with 1 or 0, we only take every next 2nd column, and multiply by ±1, ±2, or 0, to obtain the same results. Radix-4 booth encoder performs the process of encoding the multiplicand based on multiplier bits. It will compare 3 bits at a time with overlapping technique. Grouping starts from the Lower bit (LSB), and the first block only uses two bits of the multiplier and assumes a zero for the third bit as shown by figure 3.
Process for Radix-4 Booth Multiplier
RoBA Multiplier
Approximation can be performed using different techniques such as allowing some timing violations (e.g., voltage over scaling or over-clocking) and function approximation techniques (e.g., modifying the Boolean function of a circuit) or a mixture. Approximate multiplier designs mainly use three approximation approaches:
The main idea behind the proposed approximate multiplier is the make use of the simplicity of operation when the numbers are two to the power n (2n). To elaborate on the operation of the approximate multiplier, first, let us denote the rounded numbers of the input of A and B by Ai and Bi, respectively. The multiplication of A by B may be rewritten as
A*B= ((Ai-A)*(Bi-B)) + (Ai*B)+(Br*A)-(Ai*Br)
Carry select adder has less area than carry look-ahead adder but it is slower than carry look-ahead adder [8]. Carry select adder requires more area and consumes more power as compared to ripple carry adder but offers good speed. Adders in circuit gain vast area and consume large power as large additions are done in advanced processors and systems [6]. A new adder i.e., SQRTCSLA is used in many digital systems, here independently generating multiple carries and then selects a carry to generate the sum. Although the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input Cin=0 and Cin=1, then the final sum and carry are selected by the multiplexers as proposed by O.bedriji [12].The SQRTCSLA has been chosen for as it has a more balanced delay, and requires lower power and area.
As RCA is the basic adder which is used in every adder design. In CSA, each stage consists of two ripple carry adders and a set of multipliers [13]. Based on previous carry input, the present sum and carry for the next step is calculated. As the bit length of the input data to the adder increases, the number of steps of CSA also rises. In linear CSA, equal number of input bits are used in all the steps. The CSLA can be designed (proposed) as below
As the conventional CSLA adder uses two RCA for the design of SQRTCSLA. The computation speed of N-bit RCA is slow because output of each full adder is obtained whenever the previous carry is available [1].So as instead of the conventional adder I am going to use SQRTCSLA with Binary to Excess-1 Converter (BEC). The purpose of using BEC is to have low area and power. By using Binary to Excess-1 Converter (BEC) instead of RCA with Cin=1 in the conventional CSLA to achieve lower area and power consumption [7]. The advantage of BEC-1 logic is the lesser number of logic gates than the n-bit Full Adder (FA) structure.
Due to less logic gates used in BEC, there will be less area and power consumption. The SQRT-CSLA has been chosen for comparison with the conventional design as it has a more balanced delay, and requires lower power and area. As RCA is the basic adder which is used in every adder design. In CSA, each stage consists of two ripple carry adders and a set of multipliers [13]. Based on previous carry input, the present sum and carry for the next step is calculated. As the bit length of the input data to the adder increases, the number of steps of CSA also rises. In linear CSA, equal number of input bits are used in all the steps.
The adder used in the FIR Filter design in this is SQRT-CSLA that is designed with RCA-BEC based. Where Cin=0 logic is given to the RCA (Ripple carry adder) and logic Cin=1 is replaced by the BEC logic as for example a 16-bit adderusingBEC is shown in the below Fig 5. Where as the bit input for the BEC in increased by one bit every time i.e; firstly 3-bit BEC is used next it gets added by 1-bit and so on.
An FIR filter it not required feedback-based inputs, which means, this filters is not multiplied any negotiating errors in summing and multiplication. An FIR filter is naturally stable to produce output values and it can be no maximum value impulse response Nth order times, it can easily design and also easily con-figure sequence of linear phase coefficient, it will also applicable to detect the phase sensitive applications such as crossover filter design, mastering, seismology and data communications. In this filter to meet the coefficient specification in certain things, which can be suitable with time domain and frequency domain. The main disadvantages of FIR filter design are more power consumption and large area size is required for multipliers, adders and delayed element in number of Nth order based TAP. In the High performance, FIR Filter architecture will have MCM multiplication and normal adders it will perform inherently pipelined and produced the results on significant way with save computation results.
The MCM multiplier will not identified the Signed and Unsigned operation of inputs,and not concentrate on Carry operation inside of Partial Product Addition. In the FIR filter, design will take large area and take the rigid order to meet frequency range with high performance.
In this section, we have compared the area, delay and power of different multipliers as shown in table 2 below and also FIR filter design using different multipliers and SQRT-CSLA. These are been coded in VerilogHDL language and the simulation and synthesis results are obtained in XilinxISE 14.5 of family VIRTEX4 and Device
Comparision of Fir Filter Using Different Multipliers
The Vedic multiplier occupies 75 slices and 201 LUT’s less than that of Array multiplier with delay reduction of about 3.635 ns and consumes 0.013w less than that of array multiplier.
The Booth’s multiplier occupies 1945 slices and 3629 LUT’s more than that of Vedic multiplier with delay increment of about 28.258ns and consumes 0.001w more than that of Vedic multiplier.
The RoBA multiplier occupies 1270 slices and 2323 LUT’s more than that of Vedic multiplier with delay increase of about 56.761ns and consumes 1.693w more than that of array multiplier.
We have computed the area, power or delay for the FIR filter design using different multiplier with 64-bit input lengths. We have developed HDL code for each module for
input bit length. Figures 7, 8 and 9 show the area. delay and power analysis of different multiplier architecture for 64-bit input length. The below figures shows the performance analysis of FIR filter design using all the multipliers. The graphs are plotted based on the slices and LUT’s, Delay(ns) and Power consumption (W) utilized for all the multiplier blocks in FIR filter design.
Hence, FIR Filter using Vedic multiplier of bit size 64-bit utilizes less area, delay, and power consumption compared with Array, Booth’s and RoBA multipliers.
In this paper, Vedic multiplier is used to perform the multiplication operation for the FIR filter as this multiplier is appropriate for multiplying large number of bits in parallel. By comparing Vedic multiplier over different multipliers like Array, Booth’s and RoBA. Vedic multiplier is more suitable than all the multipliers.
The synthesis results demonstrate that the Vedic multiplier delivers low area, delay and lower power is obtained as compared to other multipliers. The hardware complexity of Vedic procedure is less than the other multipliers. From the obtained results, the FIR filter with Vedic multiplier acquires low area and low power than FIR filter using other multipliers.
In future work, the filter design are improved for fixed applications by using parallel-prefix adder unit in Multiple Constant Multiplication (MCM) structured and its synthesis results are compared with the present works.
Performance Analysis of Fir Filter Design Using Vedic Multiplier With Sqrt Based Carry Select Adder. (2024, Feb 22). Retrieved from https://studymoose.com/document/performance-analysis-of-fir-filter-design-using-vedic-multiplier-with-sqrt-based-carry-select-adder
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