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Micro-processors are complex electronic systems acting as the control and processing center for the machine they are embedded inside, hence, acting as their brain for the body. But, military grade processors are in a totally different league, other than being way more precise in precision and calculations, they are comparably faster than the general purpose micro-processors and DSP’s available in the general market due to their sole purpose of acting for a specific application or task, hence acting as an Application Specific Integrated Circuit (ASIC).
This paper presents the full design methodology for two 16-bit multi-cycle micro-pipelined microprocessor cores in VLIW architecture, which can function as parallel co-processors in a single microprocessor or as independent microprocessors.
Both processors are built using the Built-in-self-test (BIST) using VHDL in Xilinx ISE Design Suite 14.1.
Most importantly, this paper presents a new approach generic approach for all the radix in the Cartesian, Polar, Cylindrical, Circular and Homogenous system of co-ordinates respectively and a new approach for rotation and vectorising modes to compensate for the changing and non-constant multi and scalar factors by use of signed digits along with competitive behavior in between adders and shifters.
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The proposed approach requires the use of micro-pipelining along with an SIMD natured ISA.
Also, the results of using VLIW architecture, multi-cycle data-path along with the concept of IOPS on processors with a smaller precision order of 16-bit or lower and how the performance results indicate the greater performance and precision as compared to larger precision 32-bit and 64-bit processors.
Application Specific Integrated Circuits (ASIC) are application specific and oriented micro-processors.
These complex electronic systems are used for processing and control of complex machines requiring very fast and specific precision results to perform the required task. COordinate Rotation Digital Computer (CORDIC) are ASIC used for high precision calculations of co-ordinates, exponential, logarithmic, general arithmetic and floating point calculations. In this context, this paper describes the full design methodology for a Single Instruction Multiple Data (SIMD) and VLIW architecture based multi-cycle micro-pipelined microprocessor cores for CORDIC. The overall processor has been segmented to provide two individual microprocessor cores, the reason for which is explained later in the results.
The first core is used for co-ordinate calculations whereas the second core is used for corresponding sine, cosine, logarithmic, exponential calculations and other complex mathematical calculations for successful completion of the desired task.
In this paper, Section-II describes required mathematical equations for the respective modes for both the cores, Section-III describes the Finite State Machines (FSM) for the control unit, Section-IV describes the co-ordinate processing core, Section-V describes the complex mathematical calculation core, Section-VI shows the simulation results along with core properties and finally Section-VII includes the conclusion and preferable application areas.
CORDIC or Volder’s algorithm is a type of digit by digit algorithm i.e. it converges the obtained result by a single or more number of depending on the order or radix. It is also included in shift and add algorithms as it merely uses addition, subtraction, lookup-table and bit shift operations to perform pseudo multiplication, division and factor combining to achieve the desired result.
This algorithm can be applied for operations of complex nature in Cartesian, cylindrical, circular, and homogenous co-ordinate system to perform hyperbolic, trigonometric, logarithmic, basic arithmetic and exponential calculations.
CORDIC algorithm works by following steps:
Xn = X0 cos (ø) – Y0 sin (ø)
Yn = Y0 cos (ø) + X0 sin (ø)
The basic rotator gives the rotated co-ordinates as:
X’ = X cos (ø) – Y sin (ø)
Y’ = Y cos (ø) + X sin (ø)
Which can be rewritten as follow:
X’ = cos ø. [X - Y tan ø]
Y’ = cos ø. [Y + X tan ø]
By letting x’ and y’ be calculated iteratively, we can define the angle to be taken in each iteration as:
Tan (ø) = +2-i
= -2-i
Thus, for every “i” iteration we have:
Xi+1 = Ki [Xi – Yi. Di. 2-i]
Yi+1 = Ki [Yi + Xi. Di. 2-i]
Where,
Ki = cos (tan-1 2-i)
= 1 / √ (1 + 2-i)
= (√ (1 + 2-i))-1
Di = +1
= -1
And the calculated angle for each iteration is
Zi+1 = Zi – Di. Tan-1 (2-i)
The implementation of the algorithm requires presences of following two modes respectively, the need for which is explained in the section containing the FSM.
This mode is particularly used initially to find the set of initial co-ordinates desired or set to achieve and convert them to corresponding vector notation and perform general arithmetic or to send for processing by the next core in rotation mode.
Eq.s for Vector Mode
Xi+1 = Xi – Yi. Di. 2-i
Yi+1 = Yi + Xi. Di. 2-i
Zi+1 = Zi – Di. Tan-1 (2-i)
Where Di = +1 if Yi < 0
= -1 otherwise
Then:
Xn = An√ [(X0)2 + (Y0)2]
Yn = 0
Zn = Z0 + tan-1 (Y0 / X0)
An = ∏n √ (1 + 2-2i)
This mode is particularly used for performing the required mathematical calculations be it trigonometric, hyperbolic, arithmetic, logarithmic or exponential on the acquired sets of vectors to achieve the desired result.
Eq.s for Rotation Mode
Xi+1 = Xi – Yi. Di. 2-i
Yi+1 = Yi + Xi. Di. 2-i
Zi+1 = Zi – Di. Tan-1 (2-i)
Where Di = +1 if Yi < 0
= -1 otherwise
Then:
Xn = An [X0 cos Z0 – Y0 sin Z0]
Yn = An [Y0 cos Z0 – X0 sin Z0]
Zn = 0
An = ∏n √ (1 + 2-2i)
The mathematical core is responsible for computing complex mathematical calculations of hyperbolic, trigonometric, arithmetic, logarithmic and exponential nature. Since, it is involved in such complex calculations, it too requires multiple data entities at the same time which may be present in the form of complex numbers, or some other mathematical form and hence it too uses a micro-pipelined structure with a multi-cycle data-path.
The designed core find its applications in aerospace and military processing cores as they require calculations of complex nature where the input present might not be available in the desired format, in such a situation, the designed core or cores of such nature provides results of much greater precision and that too at the required rate and speed.
This paper concludes and provides design methodologies for improving and getting the maximum throughput from the microprocessors present in today’s market and also reducing the net time to market or finished product as a consequence of rapid prototyping.
The proposed methodology of SIMD nature, VLIW architecture, micro-pipelining, multi-cycle data-path, multiple IOPS and increased CPI, all these characteristics are applied with the aim to find its applications in ASIC and FPGA cores, within specific industries like aerospace, military, artificial neural networks and other high precision speed calculation industries requiring parallel processing concepts, and development of the ideal cores which lacked the technology at their respective times.
16-bit Micro-Pipelined Radix-II CORDIC Cores: Design and Implementation. (2024, Feb 18). Retrieved from https://studymoose.com/document/16-bit-micro-pipelined-radix-ii-cordic-cores-design-and-implementation
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