Program Northwestern University Essay
Program Northwestern University
It is May 1992. HAL, Inc. is a major manufacturer of computers and computer components. In their Lubbock, TX plant they make printed circuit boards (PCB’s, also referred to as “panels”), which are used by other plants in the company in a variety of computer products. The Lubbock plant, built in 1982, represents an $80 million investment and has approximately 450,000 square feet of manufacturing space. The plant runs 3 shifts per day (19. 5 hours/day when breaks, lunches and shift changes are considered) and makes two families of products:
1. Small Panels: 10″ x 15″ panels are the original product of the facility and are used primarily for mainframe computer cards. There are roughly 40,000 different types of small panels, most of which are made for replacement parts in older computers. The overall demand for small panels is gradually declining. 2. Large Panels: 19. 5″ x 24″ panels are a newer product, introduced in 1987, used primarily for personal computer cards. The larger size serves to reduce the cost per card and therefore most new cards are produced in this format.
There are currently about 150 different types of large panel, but this number is steadily increasing. Both product families go through the following basic sequence of manufacturing operations: • Treater Process: woven fiberglass cloth is impregnated with epoxy to make “prepreg,” the insulator used in multi-layer printed circuit boards. • Lamination-Core: layers of copper and prepreg are pressed together to form cores (blank boards). There are 8 different core blanks, from which all of the finished boards are made. •
Machining: the cores are trimmed to size. • Internal Circuitize: through a photographic exposing and subsequent etching process, circuitry is produced in the copper layers of the blanks, giving the cores “personality” (i. e. , a unique product character). • Optical Test and Repair-Internal: the circuitry of the cores is scanned optically for defects, which are repaired if not too severe. • Lamination-Composites: circuitized boards are pressed together into multi-layer boards. • External Circuitize: using the same photographic exposing and etching process
used to expose cores, circuitry is produced in the copper layers on the outside of the laminated boards to provide additional layers of circuitry. • Optical Test and Repair-External: the circuitry of the external layers is scanned optically for defects, which are repaired if not too severe. • Drilling: Holes are drilled in the boards to connect circuitry on different planes. 1 ? Wallace J. Hopp 1996 HAL, Inc. • Copper Plate: the boards are run through a copper plating bath, which deposits copper inside the holes, thereby connecting the circuits on different planes. •
Pro-Coat: a protective plastic coating is applied to the boards. • Sizing: boards are cut to final size. In most cases, multiple cards are manufactured on the same board and are cut into individual cards at the sizing step. Depending on the size of the card, there could be as few as two cards on a panel, or as many as twenty. • End-of-Line-Test: an electrical test of each board’s functionality is performed. Some of these processes (specifically Treater, Lamination, Copper Plate) are shared between the two product families. This means that sometimes a job of one board type will be delayed while it waits for a shared resource.
Because of volumes and because it is difficult to switch between the two panel sizes, the other processes have been dedicated to a single product family (e. g. , there are separate circuitize lines for 10 x 15’s and and large panels). Before 1990, the Large Panel Line had such low volumes and such a small range of part numbers that it was not a major problem. Order acceptance and scheduling were handled by the Production Control Department. The Manufacturing Engineering Department kept track of capacity data and studied equipment and process improvements.
The Manufacturing Department ran the line and, because the number of products was small, became accustomed to a de-facto rule of running only one part number per day on a process. This made managing the line easy, since few changeovers were required, demand for consumables was predictable, and operators could develop a rhythm. By 1990, however, the number of large panels had increased to around 150 and the de-facto rule of “one product per day” was no longer viable (although managers and operators were still fond of citing it as a goal).
Capacity was estimated by Manufacturing Engineering to be more than 2000 panels per day, but a more typical daily output was around 1400 panels per day. 2 In addition, although the actual amount of processing time required to make a printed circuit board was less than two days, manufacturing cycle times had steadily grown over time and were averaging close to 34 days at this point in time and customer service (the fraction of orders delivered on time) was running at about 50%. The number of (standardized) boards in the line had averaged about 47,600 in recent months.
Just prior to these events, the HAL Corporation had begun promoting the use of just-in-time concepts within its plants. Linda Brown, an internal consultant, was charged with implementing JIT in the Lubbock plant. She chose to concentrate on the more established 10 x 15 Line and wrote several documents describing basic JIT principles, held workshops with the personnel in charge of the line, and gave frequent reports to upper management on the sorry state of the line. However, Linda was promoted to a position outside the Lubbock facility before any concrete action plan was evolved. No attention at all was devoted to the Large Panel Line.
The net result was that the Lubbock management team was left with a deep cynicism about the applicability of JIT to their system. In the fourth quarter of 1990, a new plant manager, Salvatore Petitto, took over the plant. Convinced that the plant was producing well below its capacity, he summarily increased the target capacity for the large The capacity calculations made by Manufacturing Engineering were complicated by the fact that different boards required different amounts of processing at different stations. To compensate, complexity factors were defined, which represented the number of standard panel equivalents of a given board.
This was done by arbitrarily defining one of the of the boards to have a complexity factor of 1. 0 and then defining the complexity factors of the other boards to be the ratio of time required at Drilling to that required by the standard board. For instance, a board that required twice as much time at Drills as the standard board would have a complexity factor of 2. 0. This system was chosen because it was generally felt that Drills was a bottleneck. However, because rates of other processes were also a function of board type, it was recognized that the bottleneck would “float.
” Considerable controversy about the identity of the “true bottleneck” existed among the managers and engineers. 2 HAL, Inc. panel line by 50% to 3000 panels per day. He also instituted a policy of holding a 4:00 meeting of all first line managers and directly confronted those who failed to make throughput numbers or had excessive WIP in their sectors. Petitto’s major focus was on throughput, but he was also concerned about WIP, cycle time and customer service. Not surprisingly, these meetings were heated and involved a great deal of finger pointing.
Some specific issues that were raised included the following: • Manufacturing consistently held that the schedules prepared by Production Control were a joke. Production Control responded that they were merely using the customer orders (customers were exclusively other HAL plants that “stuffed” the raw circuit boards) and the approved MRP system to generate releases and due dates. The problem, they contended, was that Manufacturing constantly perverted the schedule (by means of expediters who re-prioritized work already in the plant) to try to meet the needs of high-priority customers. •
Production Control contended that the real problem with scheduling was that the plant maintained a 20-day frozen zone (i. e. , customers could not change their orders within 20 days of the due date) but cycle times were 34 days. As a result, releases had to be made to forecasts. Because forecasting was often poor, the wrong products were often released. To reconcile production with what was actually needed, Production Control held a scheduling meeting every day at 10:00. At this meeting, they looked at what quantities of various products were actually out on the floor and matched these to imminent customer needs.
Then they expedited those that were needed and “put aside” those that weren’t. In addition to frequent expediting on the shop floor, this resulted in a large quantity of WIP stacked out in the hall waiting to be reattached to a customer requirement in order to resume production. • No single process center was a consistent source of the majority of trouble. During one interval, the Copper Plater was down for almost two weeks, building a huge queue and ruining schedule performance. Soon afterward, a large buildup of WIP occurred at Drills.
Then a problem with two of the Lamination Presses caused the line to run out of the appropriate core blanks, so that although there was plenty of WIP in the line, the WIP required to meet schedule was not available. This type of occurrence was cited as evidence that the bottleneck “floated”, making the line exceedingly difficult to manage. • Some of the line managers complained that they were understaffed. Procoat, in particular, had five expose machines, but only enough operators to staff four of them. Mr.
Petitto did not rule out additional staffing, but he wanted some reassurance that more people were needed. Even with adjustments for the reduced staffing levels, the LPL seemed to be running well below capacity. • Manufacturing complained that the capacity numbers generated by Manufacturing Engineering, now at 3000 panels per day were unrealistic. However, when engineers from Manufacturing Engineering demonstrated their calculations, involving rate data from the equipment manufacturers adjusted by 14 different detractors (setups, operator efficiency, down time, yield loss, etc.
), Manufacturing personnel were unable to give convincing arguments as to why these numbers were unreasonable. But, they argued, 3000 (standard) panels per day must be wrong since this rate had never been achieved in the history of the Large Panel Line. Mr. Petitto countered that this merely showed that Manufacturing was not doing its job. Moreover, he contended that if the target rate were reduced, workers wouldn’t have incentive to strive to get better. • Managers in Circuitize complained that the continual evolution of the products prevented them from stabilizing their processes.
As one of them commented, “As soon as we get decent yields for boards with n lines per inch, we get products with 2n lines per inch and our problems start all over again. ” • Managers in End-of-Line Test complained that there had been periods of high yield loss and/or rework due to problems that should have been caught earlier in the process. As one of them pointed out “When we lose a finished multi-layer board, we’re throwing away something like $200. It would have been more like $2 if we’d caught it at the core blank level, or $20 if we caught it at the first pass
HAL, Inc. through Circuitize. ” Everyone agreed that the extreme pressure to get volumes up might be encouraging people to push work through rather than stop it for anything other than the most glaring quality problems. • Almost everyone felt that the uneven demand placed on the Large Panel Line by the board stuffing plants made managing the line difficult. Every year, the line experienced a slow period in January and early February, during which it was difficult to find enough work to keep the workers busy.
By March, however, demand would jump, the line would get overloaded, and the cycle of costly overtime and, with a few minor lulls, capacity vendoring would start again and continue through December. 2. Data As part of the ongoing discussion about the capacity of the Large Panel Line, a team of engineers from Manufacturing, Manufacturing Engineering, and Production Control compiled a set of capacity numbers for the processes that represented their best estimate of the current status of the processes
representing the basic flow through the Large Panel Line. 3 All capacities are expressed in “panel equivalents” (e. g. , they consider the fact that Core Lamination must press multiple cores to make a panel). The Treater process is not included in this data because (a) it had ample capacity and (b) prepreg was produced in bulk and stored as raw material inventory and therefore its production was not part of the cycle time required to produce panels. The numbers, summarized in Table 1, are defined as follows: •
Number of Machines: the number of tools, generally identical, in a given process center. • Base Speed: the rate of a single machine in panels per hour without any detractors. • Efficiency: the fraction of time a machine is functional, when it is not failed or being set up. Thus, the actual rate of the machine is the base speed times the efficiency. This reduction is due to other detractors besides setups and failures (e. g. , operator breaks, quality issues, etc. ). •
Lot Size: the average number of panels run between setups. Note that panels are also moved between stations in these same lot sizes. • Setup Time: the average setup time between lots, in hours. • Mean Time to Failure: the average time until a machine fails, in hours. • Mean Time to Repair: the average repair time of a machine, in hours. • Non-bottleneck Time: additional time required at a process beyond that needed for processing at the bottleneck operation of the process. For operations consisting of a single step (i.
e. , everything except the Circuitize and Procoat processes) this extra time represents the minimum time needed to move a job into the process from the upstream process. For the Circuitize and Procoat operations, the above numbers (no. machines, base speed, etc. ) refer only to the operation that defines the capacity of the process (i. e. , the bottleneck operation). The non-bottleneck time represents move time plus the minimum time needed to process a batch through all other operations besides the bottleneck process.