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Fram Based Tmr Triple Modular Redundancy For Fault Tolerance Implementation Computer Science Essay

The chief aim of this paper is to plan a Triple modular redundancy trial bench utilizing FRAM based memory faculty for OBDH ( On Board Data Handling ) system of LEO Satellite that enables the fast sensing of mistake when implied with FPGA and provides more realistic and tolerant manner of mistake happening for Single Event Upset ( SEU ) in extremely radiated infinite environment. The range of paper embraces an execution of trial bench, package algorithms, functional simulation, clocking simulation and decision of comparing of FRAM based memory faculty with EPROM and Flash Memories for mistake determination and tolera.

Mistake tolerance is the capableness of a system to get by with inside mistakes and accomplish its undertaking right. The thought of mistake tolerance is to hike the dependence of a system. A complementary but separate attack for lifting dependability is fault disincentive. inherent in the account of mistake tolerance is the predication that there is a specification of what makes up right public presentation.

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A prostration occurs when a existent running system diverges from this peculiar behaviour. The ground of prostration is called an mistake. An mistake characterizes an invalid system province, one that is non acceptable by the system behavior demands. The mistake itself is the result of a weakness in the system or mistake.

Consequently, mistake is the nucleus cause of a system failure. That means an mistake is simply the mark of a mistake. A mistake might non basically ensue in an mistake, but the same mistake may outcomes in legion mistakes.

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Similarly a individual mistake may escort to legion failures.

on the route to clear up triple-modular redundancy, it is ab initio necessary to explicate the thought of ternary redundancy, originally envisaged by Von Neumann. [ 4 ] The thought is shown in Fig. 1, where the three boxes taged with A, B and C severally are indistinguishable units or black boxes that have a individual end product and hold digital equipment. ( A black box may be a complete Personal Computer, or it can be a much less complex device, e.g. an adder or a gate. ) The ring labeled Voter is termed a “ bulk organ ” by Von Neumann. It is refered as a vote circuit since it admits the input by the three beginnings and brings out the bulk appraisal as an end product. Since the end products of the three boxes are binary and the figure of inputs is uneven, there is bound to be an expressed bulk sentiment. The three systems perform a process and the consequence is processed by a vote system to make a individual end product. If any one of the three systems falls short, the other two systems can rectify and cover the mistake. The mistake circuit turns high whenever any one of the end product diverges from the other two ; its end product can be processed to command an car refresher circuit that corrects the mistake by altering the contents of the single box bring forthing an mistake.

Figure 1: Block diagram of a TMR circuit [ 4 ] .

Why FRAM

The grounds to utilize FRAM as a storage in memory faculty of OBDH system can be inferred from properties of comparing between FRAM, EPROM and Flash that are depicted in table-1 which describes, FRAM ( Ferroelectric random ) entree memory combines fast read/write entree nature of Dynamic RAM ( DRAM ) with the ability to stay non-volatile and extremist low power ingestion ( compared to EEPROM and FLASH ) . In malice of the name, FRAM is non affected by magnetic field because there is no ferric ( Fe ) stuff nowadays in the bit. FRAM is being used in several applications particularly in infinite industry because of the robust nature of FRAM compared to other two memories i.e. FLASH and EEPROM, as shown in table-1 ; one can easy acquire the thought of optimum dependability, velocity, security and low power ingestion of FRAM [ 1 ] [ 5 ] .

Table 1: Properties of comparasion

Purpose of TMR Redundancy in OBDH

Since the TMR strategy will be deployed in the LEO Satellite OBDH system, the chief OBDH driver is present in the FRAM that is commanding the overall operations of OBDH system and OBDH subsystem itself is roll uping the monitoring informations of all other subsystems utilizing this driver. So it is much needed to on a regular basis keep the holiness and rightness of driver informations nowadays in the FRAM, and here originate the construct of ternary modular redundancy that is implemented through the development of this TMR trial bench.

Hardware description.

The Block diagram of whole TMR paradigm trial bench is depicted in figure-2 ; from the figure we can see that the trial bench is divided in three bomber blocks

Microcontroller block/Microprocessor block.

FPGA block

Memory block

Microprocessor/Microcontroller block

For the development of chief trial bench we have to utilize Microprocessor block, but for the interest of simulation we have used Microcontroller board alternatively of Microprocessor board. We are utilizing PIC18f8086 for this trial bench. The Controller is mounted on a female heading over the chief accountant board, besides the chief board have six female headings on which degree convertor PCBs are mounted because FPGA and FRAM both are non tolerant to 5V Therefore degree convertor PCBs convert 5V to 3V and frailty versa _______________________________________________________________________

FPGA Block

FPGA block is used between Microcontroller and FRAM blocks, because it is moving as a go-between to put to death the developed combinable logic of voting circuit and mistake sensor circuitry. The FPGA block is roll uping the stored driver informations from FRAM, and so checks the rightness of supplied informations utilizing the enforced combinable logic ( Voting and mistake sensing ) .

Combinational Logic execution

As discussed above we have to plan two logic circuits in FPGA, a elector circuit and an mistake circuit, so we start with the development of a “ truth tabular array ” , and so cut down the end product looks utilizing “ Karnaugh Map ” . The concluding measure would be the execution of logic from the simplified end product look and executing on FPGA utilizing Verilog codification.

Truth Table:

A

Bacillus

C

Volt

Tocopherol

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

1

1

1

1

1

0

0

0

1

1

0

1

1

1

1

1

0

1

1

1

1

1

1

0

Figure 3: Truth table demoing logic provinces of the elector and mistake circuit

Figure 3 shows the end product of the elector ( V ) and mistake circuit ( E ) for all the possible input conditions ( A, B, C ) . The elector circuit produces the correct end product by look intoing bulk input reachings i.e. the end product over which two or more systems bring forthing same end product, if any of them disagrees the mistake circuit depicts the mistake by bring forthing a high.

The simplified look for elector circuit is:

V = AB+BC+AC — — — – ( 1 )

The simplified look for mistake circuit is:

E = A B + A C + B C — — — — ( 2 )

FPGA acquires three input control Signals alongwith bidirectional Read/Write ( informations ) signal from accountant board, while 27 Pins of FPGA are being used to link 8-bit I/O information pins and 3 control pins to each of three FRAMs.

Memory Block

Memory block consist of 3 FRAMs, each comprising of 512KB memory size. Memory block is taking common control signal from FPGA and for each memory bit a separate information coach is interfaced with FPGA. The common control signal generated by FPGA is commanding the read/write operation of three memory blocks. The chief memory board comprises of three female headings over which three FM22L16 FRAMs are mounted.

Figure 2: TMR Design

Software and Program Description

Again see here the image shown in Figure-2. The processor faculty and FPGA faculty require microcode driver and verilog codification design severally. Flow chart of package description of Firmware is elucidated in general flow diagram in figure-5. In this algorithm, Processor unit ( controller unit ) initializes its variable and delaies for information package through consecutive port from Personal computer Equally shortly as the accountant gets the bid informations from Computer, and decides whether it is a read bid or a write bid? Suppose if finds it a read bid from computing machine so processor unit generates read, write and bit choice control signals and sends them to FPGA for reading of informations from the specified locations defied in the read bid from Personal computer. The information package that was sent from Personal computer contain information about start of package, bid of operation, get downing reference from where informations would be started to hive away in memory or read from memory, length of memory references to be read from FRAM, information bytes ( for write operation ) and eradicator ( Packet End ) ad shown in figure-4

Start

Low-level formatting

Condition

Read Command

Write Command

Delay for

Input Data

Figure -5: General Flow Chart for Firmware demo

.

Figure 4: Data packages for write and read operation

TMR operation is done during the read rhythm of operation. A verilog codification is implpemented for TMR operation of the design logic i.e. ; for read operation informations coming from all three memories are gathered in FPGA which so are compared amongst each other by executing spot wise comparing as defined in equation ( 1 ) and ( 2 ) and transportations correct informations to processor unit, which so sends the consequence to Computer show. In instance of write operation, FPGA will get informations from processor unit and merely hive away at peculiar memory location.

Write rhythm comparing

A functional simulation utilizing Verilog is shown in figure-6, it can be seen from figure 6 that for write rhythm the transmittal hold of FPGA is nil and we could be deceived from the response that transmittal hold is zero.

Figure 6: FPGA functional simulation of write rhythm where as in figure-7 ( clocking simulation ) it can easy be seen that the transmittal hold is 9050 PS ( 9.05ns ) .

Figure7: Verilog Timing simulation of write rhythm

Read Cycle Comparison

Similarly for read operation of functional simulation no transmittal hold is shown in figure 8. where as in clocking simulation of Read rhythm operation the hold produced by FPGA is approx 9797ps ( 9.7ns ) as shown in figure 10

Figure8: functional simulation of read rhythm

.

Figure10: timing simulation of read rhythm

Decision.

In this paper we have developed an FRAM based TMR testbench for proving the holiness of OBDH driver nowadays in FRAM, each FRAM contains the same driver informations, this testbench checks the rightness of OBDH driver informations in FRAM block and if found that any of the input provided from three input systems ( FRAMs ) is different than other two inputs, it halts the accountant and dismay for false input nowadays at any one of the input, so it takes the right driver informations from last saved driver information at some other memory location and put the information on false founded address locations of FRAM, therefore giving us a manner of rectifying an mistake and smooth operation of driver informations. The chief combinable logic for look intoing the information is implemented utilizing FPGA based vote and mistake sensing mechanism. The PIC accountant block was used to roll up the proving bids from Personal computer. This paper provides a suited and simplest architecture of TMR of memory faculty that could be used in radiated infinite environment and besides deduction of FPGA in a ternary modular system ( TMR ) makes it possible to implement a mistake tolerant technique of “ bulk ” vote system, mistake sensing and rectification and still keep fast read write rhythm of FRAM easy every bit good. From the analysis of above functional and timing simulations provide the cogent evidence that the transmittal hold of FPGA is Much less so memory entree clip which is 55ns [ 5 ] , [ 6 ] , [ 7 ] maintain TMR operation and fast read write rhythm performed accurately and right by this TMR design.

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Fram Based Tmr Triple Modular Redundancy For Fault Tolerance Implementation Computer Science Essay. (2020, Jun 02). Retrieved from https://studymoose.com/fram-based-tmr-triple-modular-redundancy-for-fault-tolerance-implementation-computer-science-new-essay

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