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Densely Packed Decimal Encoding Computer Science Essay

Paper type: Essay
Pages: 20 (4917 words)
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In the existent universe people largely use denary arithmetic ; nevertheless present twenty-four hours digital electronics is based on binary signals therefore digital computing machines perform merely binary arithmetic. Recently in applications such as fiscal and commercial, denary arithmetic at machine degree has received many involvements. Decimal notations are strongly being used for machine input-output and this gives a clear indicant that users prefer to utilize denary arithmetic. This penchant is because of the applications that require really precise computation which can non be supported by binary arithmetic as denary fractions are non supported really good here every bit far as preciseness is concerned.

For illustration, the value of 0.1 in binary requires infinite repeating binary fractions. In contrast, a denary figure system can stand for 0.1 exactly. The package execution of denary arithmetic eliminates these transition mistakes, but it is typically 100 to 1000 times slower than binary arithmetic [ 2 ] .

The most common encryption that is widely used for denary informations is Binary Coded Decimal Encoding ( BCD ) in which a individual decimal figure is represented by four spots.

The usage of operands in this encryption simplifies the denary arithmetic and shifting, and both rounding to a specii¬?ed figure of figures and transitions excessively or from characters are trivial.BCD has ever remained an appropriate encryption to utilize for the storage and simple use of denary informations. However, in some state of affairss it is advantageous to utilize a more compact signifier of representation. For illustration, merely 32 BCD figures can be stored in a 128- spot hardware registry, but in the same infinite 33 denary figures along with a mark and a 4-digit advocate can be held if a more efficient representation is used. [ 1 ]

As the demand of usage of denary arithmetic in assorted calculating application is increasing the usage of denary drifting point figure in compact signifier can be a appropriate solution. Specifically, denary add-on, minus, switching, rounding, and transitions to character signifier are significantly simplified by the saving of denary digit boundaries.

Chen and Ho [ 5 ] described a strategy for encoding denary informations which is rather efficient. The Chen-Ho encryption, as it is called, compresses three denary figures into 10 spots with really small waste, giving a 17 % more compact encryption than BCD ( which uses 12 spots to hive away three denary figures ) .It uses a Huffman codification [ 4 ] , with most important spots choosing assorted digit combinations. The chief advantage of Chen-Ho encoding over binary representation in 10 spots is that merely simple Boolean operations are needed for transition to or from BCD ; generation and divisions are non required..

Another encryption technique proposed by M. Cowlishaw, Densely Packed Decimal ( DPD ) [ 1 ] , uses an tantamount encryption to the Chen-Ho strategy, but it is an betterment over Chen-Ho encryption and hence has farther advantages. The chief advantage over Chen-Ho encryption is that it is non restricted to the fact that for compaction the denary figures should be in multiple of three, which is the primary demand of Chen-Ho encryption.

The cost of deploying hardware is diminishing twenty-four hours by twenty-four hours and the important hardware issues like operation velocity and storage efficiency attracts the attending of hardware interior decorators to add a denary arithmetic unit to CPUs to execute denary computations. The recent developments in embedded systems engineering and FPGA solutions have besides motivated the usage of a separate hardware system for applications affecting fast operation velocities.

Now a yearss assorted hardware platforms are available that provide control of both logic and package codification by a soft file. Because of this, the low cost of design care and grade of design reuse is greatly enhanced. Xilinx, Alektra are some of the platform providers.The platforms available like Digilent board, Alektra Kit etc. contains FPGA to transport out design, execution, and existent clip simulation of hardware.

Softwares like the Xilinx ISE system is an incorporate design environment that consists of a set of plans to make ( gaining control ) , simulate and implement digital designs in an FPGA mark device. It offers an attractive and easy to utilize GUI along with online aid. By supplying incorporate tools for HDL entry, synthesis, execution, and confirmation in a free downloadable environment, ISE 10.1 helps users quickly achieve design ends while cut downing overall undertaking cost.

The thesis contains the execution inside informations of Densely Packed Decimal ( DPD ) encoding utilizing hardware description linguistic communication VHDL, Xilinx ISE WebPACK 10.1 for simulation, design, and execution on FPGA of mark device, Xilinx ChipScope Pro for debugging and end product and Digilent Board incorporating VIRTEX-II Pro FPGA as mark device.

Chapter 2

Literature Survey

Binary Coded Decimal Encoding

Chen-Ho Encoding

Dumbly Packed Decimal Encoding

Chapter 2

2 Literature Survey

2.1 Binary Coded Decimal Encoding

To BCD-encode a denary figure utilizing the common encryption, each figure is encoded utilizing the four-bit binary spot pattern for each figure. For illustration, the figure 127 would be:


Since most computing machines store informations in eight-bit bytes, there are two common ways of hive awaying four spot BCD digits in those bytes, each figure is stored in one byte, and the other four spots are so set to all nothings, all 1s ( as in EBCDIC codification ) or to 1011 ( as in the ASCII codification ) two figures are stored in each byte.

A widely used fluctuation of the two-digits-per-byte encryption is called “ packed BCD ” , where Numberss end with a mark ‘digit ‘ , for which the preferable values are 1100 for + and 1101 for a?’ . In jammed BCD the figure 127 would be represented as the bytes 00010010 01111100, and a?’127 as 0001001001111101.

While BCD does non do optimum usage of storage ( about 1/6 of the available memory is non used in jammed BCD ) , transition to ASCII, EBCDIC, or the assorted encryptions of Unicode is fiddling, as no arithmetic operations are required. More heavy waddings of BCD exist ; these avoid the storage punishment and besides need no arithmetic operations for common transitions.

Unlike pure binary encryptions big Numberss can easy be displayed by dividing up the nybbles and directing each to a different character with the logic for each show being a simple function

map. Converting from pure double star to decimal for show is much harder affecting integer generation or divide operations. The BIOS in PCs normally keeps the day of the month and clip in BCD format, likely for historical grounds ( it avoided the demand for binary to ASCII transition ) .

If a denary figure requires four spots, so three denary figures require 12 spots. However, since 210 & gt ; 103, if three denary figures are encoded together so merely 10 spots are needed. Two such encryptions are Chen-Ho encoding [ 5 ] and Densely Packed Decimal [ 1 ] . The latter has the advantage that subsets of the encoding encode two figures in the optimum 7 spots and one figure in 4 spots, as in regular BCD.

2.2 Chen-Ho Encoding

The Chen-Ho encryption [ 5 ] allows three denary figures to be represented in 10 binary spots, which may hold up to 1,024 possible different values, and which hence can encode the 1,000 possibilities for three figures with merely a small waste.

The advantage that is incurred from Chen-Ho encoding over a straightforward binary representation in 10 spots is that merely simple Boolean operations are needed for transition to or from BCD ; generations and divisions are non required. This encryption besides has the advantage over variable length strategies, because its fixed-length function allows simpler encryption and decryption in either hardware or package.

The Chen-Ho strategy works really good when denary Numberss have lengths which are multiples of three denary figures, as this encoding battalions three figures into 10 spots with small waste. It is less satisfactory for other lengths, nevertheless, because either figures must be wasted or more than one encryption has to be used to stand for the assorted figures of the figure.

2.3 Dumbly Packed Decimal Encoding

Dumbly Packed Decimal Encoding [ 1 ] proposed by M. Cowlishaw is an betterment over Chen-Ho encoding. It uses the coding strategy equivalent to the Chen-Ho but alternatively of utilizing Huffman-code it uses a fresh agreement of spots that gives it farther advantages over the Chen-Ho strategy. The advantages can be listed as follows: [ 1 ]

The encryption of denary figure is non restricted to the fact that the figure of denary figures ever be a multiple of three. It can encode arbitrary figure of denary figures. One or two denary figures are compressed into the optimum four or seven spots severally.

The encoded denary Numberss can be expanded into a longer field merely by embroidering with zero spots ; re-encoding is non necessary. While Chen-Ho encoding requires a re-encoding alternatively of simple embroidering if an encoded two figures is expanded into three digit field.

When Numberss in the scope 0 through 79 are encoded by this strategy they have the same right-aligned encryption as in BCD. While in Chen-Ho encoding merely the Numberss 0 through 7 remains same as in BCD.

These advantages make the new encoding a better pick than Chen-Ho encoding for both hardware and package representations of denary Numberss.

Here are some illustrations of encoding in BCD, Chen-Ho and Densely Packed Decimal [ 1 ] :

Decimal fraction



Dumbly Packed


0000 0000 0101

000 000 0101

000 000 0101


0000 0000 1001

110 000 0001

000 000 1001


0000 0101 0101

000 010 1101

000 101 0101


0000 1001 1001

111 000 1001

000 101 1111


0101 0101 0101

010 110 1101

101 101 0101


1001 1001 1001

111 111 1001

001 111 1111

Fig 1: Examples of BCD, Chen-Ho and DPD Encoding

Detailss of the encryption

The DPD encryption, categorizes each of the three figures as follows:

Small ( 0-7, necessitating 3 spots )

Large ( 8 or 9, necessitating one spot ) .

The most important spot of each BCD figure is 0 for little values, and 1 for the big values.

The possible combinations of these scopes are so [ 1 ] :

Number of little figures


Number of spots required for figures

Number of spots to bespeak combination


51.2 %




38.4 %




9.6 %




0.8 %


7 ( merely 5 needed )

Chapter 3


Design of DPD System

System Platforms

Chapter 3

3 Execution

3.1 Design of DPD System

The compaction and enlargement block of Densely Packed denary encryption system is designed as:

Compaction Block

DPD compaction faculty

Decimal to BCD convertor

3 digit denary figure

( in binary signifier ) BCD ( 12 spots ) 10bits DPD figure

For compaction, three figure denary figure is passed as input to the compression block where Decimal to BCD convertor converts the binary figure in BCD encoded figure of 12 bits.This 12 spot BCD figure is so fed to DPD compaction faculty which eventually compresses the figure and encode it in 10 spots dumbly packed denary signifier.

Expansion Block

DPD enlargement faculty

BCD to Decimal convertor

10bits DPD figure BCD ( 12 spots ) BCD ( 12 spots ) Decimal n 3digit Decimal figure

For enlargement the 10 spots DPD figure is now the input to the enlargement block where first it is expanded to BCD signifier by DPD enlargement module.The 12 spots BCD end product is so converted to denary figure in simple binary format by BCD to decimal convertor.

3.1.1 Decimal ( Binary ) to BCD convertor

Before the denary figure, which is in simple binary format, is compressed utilizing DPD encoding it is converted into BCD signifier, since DPD works upon the denary figure encoded in BCD. For transition to BCD, a BCD convertor faculty in VHDL is developed that takes 10 spots denary figure in binary format and converts into 12 spots of BCD end product.

The Binary to BCD convertor plants in following stairss [ 10 ] :

The binary figure is shifted to left by 1 spot.

Three columns are devised 100s, 10s and units of 4 spot each from left to right.As the binary figure is shifted to go forth one by one, after 8 displacements the figure is in 100s, 10s and units column with most important spot in 100s column.

If the value of figure in any of the BCD column is 5 or greater, 3 is added to that BCD column.

Measure 1 is performed once more till every spot of binary figure is shifted.

For adding three, a add-3 faculty is created which maps the value of column ( when greater than 5 ) to their added consequence ( consequence after adding three ) .

In the BCD to Binary convertor module the add-3 faculty is used as a constituent and is shown as Fig 2 in the block diagram of binary to BCD convertor Fig 3.

Fig 2 Add-3 faculty for binary to BCD convertor

Fig 3: Block Diagram of Binary to BCD Converter

3.1.2 Dumbly Packed Decimal Compression Module

Once the denary figure is converted to BCD format, it can be compressed utilizing DPD encoding.The encoding circuit is a simple combinable logic affecting 12 inputs and 10 end products and is given by following looks in VHDL [ 1 ] :

P & lt ; = ( ( NOT a ) AND B ) OR ( a AND J AND ( NOT i ) ) OR ( a AND degree Fahrenheit AND I AND ( NOT e ) ) ;

Q & lt ; = ( ( NOT a ) AND degree Celsius ) OR ( a AND K AND ( NOT i ) ) OR ( a AND g AND I AND ( NOT e ) ) ;

R & lt ; = vitamin D ;

s & lt ; = ( ( NOT e ) AND f AND ( NOT ( a AND I ) ) ) OR ( ( NOT a ) AND ( NOT i ) AND e AND J ) OR ( vitamin E AND I ) ;

T & lt ; = ( ( NOT e ) AND g AND ( NOT ( a AND I ) ) ) OR ( ( NOT a ) AND ( NOT i ) AND e AND K ) OR ( a AND I ) ;

u & lt ; = H ;

V & lt ; = a OR vitamin E OR I ;

tungsten & lt ; = a OR ( vitamin E AND I ) OR ( ( NOT e ) AND J AND ( NOT i ) ) ;

ten & lt ; = vitamin E OR ( a AND I ) OR ( ( NOT a ) AND K AND ( NOT i ) ) ;

Y & lt ; = m ;

where a, B, degree Celsius, vitamin D, vitamin E, degree Fahrenheit, g, H, I, J, K, m represents 12 spots of input BCD figure and P, Q, R, s, T, u, V, tungsten, x, y signifies 10 spots of end product DPD decocded figure.

3.1.3 Dumbly Packed Decimal Expansion Module

The enlargement or decipherer circuit is besides a simple combinable logic affecting Boolean operations.The input to the enlargement faculty is 10 spots DPD decoded figure and end product is 12 spots BCD number.The faculty is written in VHDL and contains following looks [ 1 ] :

a & lt ; = ( V AND tungsten ) AND ( ( NOT x ) OR ( NOT s ) OR ( s AND T ) ) ;

B & lt ; = P AND ( ( NOT v ) OR ( NOT w ) OR ( s AND ( NOT t ) AND x ) ) ;

degree Celsius & lt ; = Q AND ( ( NOT v ) OR ( NOT w ) OR ( s AND ( NOT t ) AND x ) ) ;

vitamin D & lt ; = R ;

vitamin E & lt ; = V AND ( ( ( NOT w ) AND x ) OR ( ( ( NOT t ) OR s ) AND w AND x ) ) ;

degree Fahrenheit & lt ; = ( s AND ( ( NOT v ) OR ( ( NOT x ) AND V ) ) ) OR ( P AND ( NOT s ) AND T AND V AND tungsten AND x ) ;

g & lt ; = ( T AND ( ( NOT v ) OR ( ( NOT x ) AND V ) ) ) OR ( Q AND ( NOT s ) AND T AND V AND tungsten AND x ) ;

H & lt ; = U ;

I & lt ; = V AND ( ( ( NOT w ) AND ( NOT x ) ) OR ( w AND x AND ( s OR T ) ) ) ;

J & lt ; = ( ( NOT v ) AND tungsten ) OR ( s AND V AND ( NOT w ) AND x ) OR ( P AND V AND tungsten AND ( ( NOT x ) OR ( ( NOT s ) AND ( NOT t ) ) ) ) ;

K & lt ; = ( ( NOT v ) AND x ) OR ( T AND V AND ( NOT w ) AND x ) OR ( q AND V AND tungsten AND ( ( NOT x ) OR ( ( NOT s ) AND ( NOT t ) ) ) ) ;

m & lt ; = Y ;

3.1.4 BCD to Binary Converter

After the decryption is over by DPD enlargement faculty, the figure is in BCD format and needs to be converted to decimal binary form.This transition is carried out by BCD to binary convertor which is developed in VHDL as a faculty that takes 12 spots BCD figure as input and produces 10 spots denary figure in binary as end product.

The convertor is developed from the thought that a BCD figure is comprised of 100s, ten percent and unit for a three figure number.Suppose the three digit figure is represented in BCD as:

( a B degree Celsius vitamin D ) ( e degree Fahrenheit g H ) ( one j k cubic decimeter ) H T O

For transition to decimal figure, say, N

N = 100H + 10T + O

To accomplish this value of ‘N ‘ undermentioned stairss are followed:

The figure ‘H ‘ is shifted to left three times

H — & gt ; 8H aˆ¦aˆ¦aˆ¦aˆ¦aˆ¦aˆ¦aˆ¦.. ( 1 )

The figure ‘H ‘ is once more shifted to go forth one clip

H — & gt ; 2Haˆ¦aˆ¦aˆ¦aˆ¦aˆ¦aˆ¦aˆ¦aˆ¦ ( 2 )

Adding ( 1 ) , ( 2 ) and figure ‘T ‘ we have,

10H + Thymine

Switching ( 10H + T ) to left three times we get,

( 10H + T ) – – & gt ; 8 ( 10H + T ) aˆ¦aˆ¦aˆ¦aˆ¦aˆ¦aˆ¦ ( 3 )

Switching ( 10H + T ) to go forth one clip

( 10H + T ) – – & gt ; 2 ( 10H + T ) aˆ¦aˆ¦aˆ¦aˆ¦aˆ¦aˆ¦ ( 4 )

Adding ( 3 ) , ( 4 ) and figure ‘O ‘ we have the concluding consequence.

80H + 8T

20H + 2T

+ O

N = 100H + 10T + O

3.2 System Platforms

The DPD system designed as described above is implemented utilizing both package and hardware platforms.Thus it can be said that the DPD system is a hardware-software codesign. The hardware and package platforms are good described in the undermentioned subdivisions.

3.2.1 Hardware Platform: Virtex-II Pro Platform

The Virtex-II Proa„?/Virtex-II Pro X Platform FPGA solution is the most technically sophisticated Si and package merchandise development in the history of the programmable logic industry.Leading squads from top embedded systems companies worked together with Xilinx package squads to develop the systems package and IP solutions that enabled the new system architecture paradigm. The consequence is the first Platform FPGA solution capable of implementing high public presentation system-on-a-chip designs antecedently the sole sphere of usage ASICs, yet with the flexibleness and low development cost of programmable logic. The Virtex-II Pro/Virtex-II Pro X household marks the first paradigm alteration from programmable logic to programmable systems, with profound deductions for leading-edge system architectures in networking applications, profoundly embedded systems, and digital signal processing systems. It allows custom user-defined system architectures to be synthesized, next-generation connectivity criterions to be seamlessly bridged, and complex hardware and package systems to be co-developed quickly with insystem debug at system velocities. Together, these capablenesss usher in the following programmable logic revolution [ 7 ] .

Each of the larger devices of the household incorporates one or two little yet powerful IBMA® PowerPCa„? 405 processor nucleuss, each capable of more than 300 MHz clock frequence and 420 Dhrystone MIPS [ 7 ] . The PowerPC 405 nucleuss are to the full embedded within the FPGA cloth, where all processor nodes are controlled by the FPGA routing resources. This provides the extreme architectural capableness, where complex applications may be expeditiously divided between high-velocity logic execution and high-flexibility package executions. The Virtex-II Pro/Virtex-II Pro Ten merchandises are based on the most advanced FPGA cloth available. The Virtex-II Pro/Virtex-II Pro X household is the first FPGA household to integrate both consecutive transceiver engineering and a difficult processor nucleus within a all-purpose FPGA device.

Fig 4: XUP Virtex-II Pro Development System Board Photo

It is important that the embedded systems enabled by Virtex-II Pro solutions are “ all-soft, ” in that both logic and package codification are controlled by a soft informations file. Because of this, the low cost of design care and grade of design reuse is greatly enhanced.

Some of the salient characteristics of Virtex-II pro development system board are shown in Fig 4.

3.2.2 Software Platform: Xilinx ISE WebPACK 10.1

The Xilinx ISE system is an incorporate design environment that consists of a set of plans to make ( gaining control ) , simulate and implement digital designs in an FPGA or CPLD mark device. It offers an attractive and easy to utilize GUI along with online aid.

ISE WebPACK 10.1 package offers a complete front-to-back FPGA design solution leting users to instantly get down undertakings. By supplying incorporate tools for HDL entry, synthesis, execution, and confirmation in a free downloadable environment, ISE 10.1 helps users quickly achieve design ends while cut downing overall undertaking cost. The assorted characteristics of Xilinx WebPACK are described below:

Xilinx ISE Simulator

Key characteristics are: –

Smart compile engineering to recognize faster run times

Tcl bid console to easy passage from the ISE package graphical user interface to a bid line environment.

Expanded incorporate Timing Closure Environment to let cross examining between clocking analyser, restraints editor and floorplan spectator for easiness in design geographic expedition of Virtex series designs

New power optimisation in Xilinx Synthesis Technology ( XST ) and arrangement, together with betterments in routing, present an norm of 10 per centum lower dynamic power for the Spartan-3 coevals of FPGAs.

Xilinx CORE Generator

The CORE Generator is a design tool that delivers parameterized Intellectual Property ( IP ) optimized for Xilinx FPGAs. The Core Generator provides the undermentioned ready-made maps which include:

A FIFOs and memories

Adders and Subtractors

FIR filters


Standard coach interfaces such as PCI and PCI-X,

Xilinx ChipScope PRO

ChipScope Pro tool inserts logic analyser, coach analyser, and practical I/O low-profile package cores straight into the design, leting the coder to see any internal signal or node, including embedded hard or soft processors. Signals are captured at or near operating system velocity and brought out through the scheduling interface, liberating up pins for the design. Captured signals can so be analyzed through the included ChipScope Pro Logic Analyzer.

ChipScope Pro Key Features [ 9 ] :

Analyze any internal FPGA signal, including embedded processor coachs

Inserts low-profile, configurable package cores either during design gaining control, or after synthesis

All ChipScope Pro nucleuss are available through the Xilinx CORE Generator System

Enhancements to the Virtex-5 System Monitor console make it easier to entree on-chip temperature, electromotive force, and external detector

Change investigation points without re-synthesizing

Chapter 4

Simulation and Consequences

Simulation Setup

Consequences and Analysis

Chapter 4

4 Simulation and Results

This subdivision presents the simulation and consequences of the Densely Packed Decimal Encoding System when implemented utilizing hardware and package platforms as discussed in subdivision 3. In the undermentioned subdivision we will see the simulation apparatus that includes stairss and processs to transport out the simulation and eventually the consequences are analyzed.

4.1 Simulation Setup

Once the all VHDL faculties are ready, they should be simulated before they are put in existent hardware. We can make a trial bench wave form from the Projecta†’New Source bill of fare of ISE and it will help in puting up the simulation.

The DPD encoder faculty when simulated utilizing trial bench with 999 as the BCD input, the simulation obtained is as shown in Fig 5.

The simulation consequence as obtained on DPD encryption is given as input to DPD decipherer and the simulation obtained is as shown in Fig. 6.

Once we simulate our design and experience it is function right, so we can travel on to bring forthing the information needed to really plan the mark device with our design.

First of wholly, make the UCF file taking aid from the user manual of the mark device..The UCF file is an ASCII file stipulating restraints on the logical design.The UCF file is required to pass on with our design which is implemented on mark device utilizing switches, push buttons, LED ‘s etc. We create this file and come in our restraints in the file with a text editor. We can besides utilize the Xilinx Constraints Editor to make restraints within a UCF file. These restraints affect how the logical design is implemented in the mark device.

Fig 5: Trial Bench Simulation of DPD encoding with 999 as BCD input

Fig 6: Trial Bench Simulation of DPD decrypting with 999 as BCD end product

The UCF file for our design contains following restraints:

Net “ CLK ” LOC = ” AJ15 “ ;

Net “ reset ” LOC= “ AC11 ” ;

Net “ burden ” LOC= “ AD11 ” ;

Net “ enable ” LOC= “ AF8 ” ;

We use Xilinx ChipScope PRO to debug and see the consequences, so we need to make a chipscope file with.cdc extension.This can be done by following stairss:

Right chink on the top faculty of the design intended for confirmation or debugging, and choice new beginning. Then choice ChipScope Definition and Connection File.

Give an appropriate file name and follow the waies. A new file ( with file name as given ) will be created in the beginning window under the undertaking hierarchy.

Double chink on this new beginning file which cause the chipscope window to start up.Follow the waies given and look into the needed settings.Select the figure of trigger ports and their several breadths depending on the design requirement.Trigger ports would enable the the start of simulation subsequently on when the design is implemented on mark device.

On Capture Parameters, uncheck the Data Same As Trigger option. Define Data Width as entire breadth of signals that will be displayed on wave form for debugging. Data Depth defines the figure of samples of tally demand to be displayed.

On Net Connections check, when Modify Connections is clicked, a window will start up. Choose the appropriate signals from the list of cyberspaces in the popped up window and do connexions to the several clock, trigger and information signals.

Once all the connexions are made imperativeness OK.Then imperativeness Return to Project Navigator and Save Project alterations.

Now we have all the necessary files available for execution on mark device.It ‘s clip to travel for synthesis and scheduling flow.

The first measure is synthesis. This is the procedure of implementing the VHDL into logic Gatess. Once that is done, the following few stairss are device and device seller specific stairss of interpreting the Gatess into physical executions of the gate functionality. For illustration, our VHDL might synthesise a 2-input AND gate, but the engineering merely has 2-input NOR Gatess. These stairss will implement the AND gate as two NAND Gatess, for illustration. Once this engineering function is done the design can be placed into the mark device and routed. Finally, bring forthing programming file will make a spot file that will really plan the device with the design.

Now double-click on the Analyze Design Using Chipscope under procedure window.this will open chief window of chip-scope pro.

First of all, chink on JTAG concatenation to observe available JTAG connexion to aim devices attached. A new bill of fare window appears, depicting the detected device. Choose the mark Device, configure it utilizing the generated plan spot file and click OK. On chink of OK ; the trigger window, the information window and the console window appear in the chief window. Click on FILE – & gt ; Import and choose the chipscope file that we had created as.cdc extension. Importing the file will alter the name of signal as per our plan in the trigger and wave form window.

Now change the trigger signals utilizing mark device switches, push buttons as mapped by UCF file and run the simulation.The changed wave form will look as influenced by alteration in trigger signals.

4.2 Consequences and Analysis

The design when simulated and implemented on the mark device, the device use consequences obtained are summarized in Fig 7

The DPD encryption of denary figure 80 ( 80 ) is simulated and the consequence obtained on chipscope is as shown in Fig 8.

The DPD decryption of encoded denary figure 80 is simulated and the consequence obtained on chipscope is as shown in Fig 9.

Fig 7: Design Summary of the DPD system ( encoding ) when implemented on mark device

Fig 8. Chipscope consequence of DPD Encoding denary figure 80.

Fig 9. Chipscope consequence of DPD decryption of denary figure 80

Chapter 5

Decision and Future Work

Chapter 5

5 Conclusion and Future Work

The thesis covers the execution of Densely Packed denary encryption and decrypting on a Virtex-II Pro development platform. The DPD system developed successfully performs compaction and enlargement of denary Numberss.

The future work may dwell of supplying runtime input to system which can be done utilizing EDK.Using the FPGA editor and Floor contriver of the ISE the system can be made more efficient in footings of infinite acquired when deployed on a existent hardware bit.

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Densely Packed Decimal Encoding Computer Science Essay. (2020, Jun 01). Retrieved from https://studymoose.com/densely-packed-decimal-encoding-computer-science-new-essay

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