We use cookies to give you the best experience possible. By continuing we’ll assume you’re on board with our cookie policy

AND/OR array Essay

Paper type: Essay

Words: 783, Paragraphs: 11, Pages: 4

Sorry, but copying text is forbidden on this website!

or Listen to your own essay

It includes flipflops within the intergrated circuit chip in addition to the AND/OR array. The circuit outputs can be taken from the OR gates or from the outputs of the flipflops. Additional programmable connections are available to include the flipflop outputs in the product terms formed with a AND array. The flipflops may be of D or JK types. Field programmable logic sequencer (FPLS) is the first programmable device to support sequential circuit implementation (Mano, 2002:283). Each section of a SPLD is called a macro cell.

A macro cell is a circuit that contains a sum of products, combinational logic function and an optional flipflops. The output is driven by an edge triggered D flipflop. The flipflop is connected to a commom clock input and changes state on a clock edge. The output of the flipflop is connected to a 3 state buffer controlled by an output enable (OE) signal. The output of the flipflop is fed back into one of the inputs of the programmable AND gates to provide the present state conditions for the sequential circuit.

A typical SPLD has 8-10 macro cells within one IC package.

Typical programming options include the ability to use or bypass the flipflops, selection of clock edge polarity, selection of preset and clear and selection of true or complement of an output. Advantages Design is traditional and hence easy. Logic utilization is very high compared to CPLDs. Disadvantages Data is propagated to the output after a considerable amount of time due to sequential data flow. The design of a digital system using PLD requires the connection of several devices to produce the complete sepcification.

The CPLD is a collection of individual PLDs on a single integrated circuit. A programmable interconnection structure allows CPLDs to be connected as in the case of individual PLDs. The general configuration of a CPLD consists of multiple PLDs interconnected through a programmable switch matrix. The IO blocks provide the connection to the IC pins. Each IO pin is driven by a 3 state buffer and can be programmed to act as input or output. The switch matrix receives inputs from the IO block and directs it to the individual macrocells.

Selected outputs from macrocells are sent to the output. The macrocells within each PLD are fully connected. The macrocell flipflop can be programmed to act as D, JK or T flipflop (Mano, 2002:286). (Lee, 2001) (Lee, 2001 ) Advantages Complex circuits can be designed easily. Disadvantages Hardware requirements are very high. Additional glue devices are required. Field-programmable parts are used for interconnection of 2 or more FPGAs. The interconnections occupy bulk space in the FPGA design.

When 2 or more FPGAs are utilized in the design, there is a requirement for glue logic for interconnection. Also, the FPGA is effectively utilized with interconnecting logic removed. The design of FPIC are frequently in competition with FPGA devices for interconnect implementation. Here, the full connectivity occurs at top level. Routing between FPGAs requires determining level at which source and destination share an ancestor. In design, the inter-FPGA signals travel through at most two FPICs.

Practically, the maximum distance in mesh topology is N0. 5 for N FPGAs. (Kyung, 2004) Advantages Simplified routing High internal connectivity Lack of connection blocks leads to fewer transistors, better performance Disadvantages Not always cost effective Exhibit expanded pin counts. Advanced configurations of FPGA also includes a state machine, or “sequencer,” which controls several global signals, i. e the signals that are broadcast throughout the FPGA. The sequencer is capable of performing a shut-down sequence that manipulates the global signals in a way that places the FPGA in a “safe” mode.

The safe mode protects against potentially destructive interconnect contention that might otherwise occur during reconfiguration, and therefore allows all or a portion of the FPGA to be reconfigured without powering down or resetting the FPGA. This process saves valuable time, particularly when only a relatively small portion of the FPGA need be reprogrammed. The sequencer can be instructed to preserve user data during reconfiguration. (Source: www. makaton-signs. org. uk/… /sequencer. jpg) Advantages

The preserved user data is then available for use by the FPGA after the FPGA is reconfigured to perform a new logic function. The need to save user data externally if any user data is to be retained for use with a subsequent configuration is eliminated. Disadvantages Choice of selection of a suitable device is very low as the technology is new and evolving.

(1) Lee, C. H. Hall, D. V. Perkowski, M. A and Sun, D. S (2001) ‘Self-Repairable GALs’. Journal of systems Architecture, Vol. 47, no. 2 , February, pp: 119-135. (2) Mano, M. M (2002) Digital Design, Third edition, Delhi, India, Prentice-Hall.

How to cite this page

Choose cite format:

AND/OR array. (2017, May 05). Retrieved from https://studymoose.com/andor-array-essay

Is Your Deadline Too Short? Let Professionals Help You

Get Help

Our customer support team is available Monday-Friday 9am-5pm EST. If you contact us after hours, we'll get back to you in 24 hours or less.

By clicking "Send Message", you agree to our terms of service and privacy policy. We'll occasionally send you account related and promo emails.
No results found for “ image
Try Our service

Hi, I am Sara from Studymoose

Hi there, would you like to get such a paper? How about receiving a customized one? Click to learn more https://goo.gl/CYf83b


Hi, I am Sara from Studymoose

Hi there, would you like to get such a paper? How about receiving a customized one? Click to learn more https://goo.gl/CYf83b


Your Answer is very helpful for Us
Thank you a lot!