An optical architecture to break ciphers Essay

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An optical architecture to break ciphers

The targeted DES brute force attack has several characteristics. To begin with, expensive computational operations which are put in parallel. Next, there is no need of communication between single parallel instances. The next characteristic is the fact that the general expense for communication is not high owing to the fact that the stage of computation strongly outweighs the data input and output stages. According to Blaze et al, (1996), communication is almost entirely used for results reporting as well as initialization.

A central control instance with regards to communication is capable of being accomplished by a conventional low cost personal computer, connected simply by an interface. This would imply that there is no need for a high-speed communication interface. The fourth characteristic is the fact that a DES brute-force attack and its following implementation require little memory. The final consequence of the above is the fact that the available memory on present day low cost FPGAs is sufficient (Guneysu, 2006).

What this implies is that by making use of low-cost FPGAs, it is possible to develop a cost effective dynamic architecture which is capable of being reprogrammed which would be able to accommodate all the targeted architectures (Blaze et al, 1996). Realization of COPACOBANA Drawing back, the Cost-Optimized Parallel Code Breaker (COPACOBANA) meeting the needs available comprise of several independent-low prized FPGAs, connected to a hosting PC by way of a standard interface such as a USB. Moreover, such a standard interface permits to extend a host-PC with more than one device of COPACOBANA.

The initialization of FPGAs, the control as well as the process of results accumulation is carried out by the host. Critical computations are carried out by the FPGAs, which meet the actual cryptanalytical architecture (Schleiffer, 2006). Developing a system of the above speculations with FPGA boards which are commercially available is certainly possible but at a cost. Therefore it is important to put into considerations the design and layout among others in coming up with the above kind of system (Schleiffer, 2006).

This would therefore mean that our cost-performance design meant for cost optimization is only capable of being achieved if all functionalities are restricted to those required for code breaking. Arty the same time, many designs choices should be based on components and interfaces which are readily available (Guneysu, 2006). Conclusion In conclusion, cryptanalysis of symmetric and asymmetric ciphers is extremely demanding in terms of computations. It would be fair to hold the belief that breaking codes with conventional PCs as well as super-computers is very much costly.

Bit-sizes of keys should be chosen in a way that traditional methods of code breaking do not succeed (Rouvroy et al 2003, pp. 181-193). This would mean that the only way to go through ciphers is to develop special-purpose hardware purposely meant for suitable algorithms. In the final analysis, traditional parallel architecture in the end equally appears to be too complicated and therefore not cost saving in finding solutions to cryptanalytical problems.

As earlier observed, many of these problems can easily be put in parallel implying that the algorithms which correspond to them are equally capable of being parameterized to lower communication costs (Guneysu, 2006). A hardware architecture which is cost effective (COPACOBANA) is the end product of the algorithmic requirements of the intended problems of cryptanalysis. This work represents not only the design but also the first prototype of an effective design which meets the demands of the request. In the final analysis, COPACOBANA would be able to accommodate as many as 120 FPGAs which are less costly.

At the same time, it is possible to break data encryption standard (DES) within a period of nine days. This would require a hardware design comprising of reprogrammable logic which could be adopted to accommodate any task, even those not necessarily in line with code breaking (Rouvroy et al 2003, pp. 181-193). References Blaze, M.. , Diffie, W. , Rivest, R. L. , Scheiner, B. , Shimomura, E. , and Weiner, M (1996). Minimal Key Lengths for Symmetry Ciphers to Provide Adequate Commercial Security. Ad Hoc Group of Cryptographers and Computer Scientists.

Retrieved from December, 13, 2008 from http://www.counterpane. com/keylength. html. Clayton, R. and Bond, M. (2002). Experience Using a Low-Cost FPGA Design to Crack DES Keys. In B. S. Kaliski, C. K. Koc Cetin, and C. Paar, editors, Cryptographic Hardware and Embedded Systems – CHES 2002, 4th International Workshop, Redwood Shores, CA, USA,volume 2523 of series, pages 579 – 592. Springer-Verlag. Conrad, E. (2007). Data Encryption Standard, The SANS Institute Diffie, W & Hellman, M. E. (1977). Exhaustive cryptanalysis of the NBS Data Encryption Standard. Computer, 10(6): 74-84 Electronic Frontier Foundation. (1998). Cracking DES: Secrets of Encryption.

Research, Wiretap Poolitics & Chip Design. O’Reilly & Associates Inc. Federal Information Processing Standard. (1977). Data Encryption Standard, U. S Department of Commerce. Guneysu, T. E. (2006). Efficient Hardware Architecture for Solving the Discrete Logarithm Problem on Elliptic Curves. AAmasters thesis, Horst Gortz Institute, Ruhr University of Bochum. Landau, S. (2000). Standing the Test of Time: The Data Encryption Standard vol. 47, 3, pp. 341-349. Lenstra, A and Verheul, E. (2001). Selecting Cryptographic Key Sizes. Journal of Cryptology, 14(4):255–293.

Rouvroy, G. , Standaert, F. X. , Quisquater, J., and Legat, D. (2003). Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES. In Field-Programmable Logic and Applications- FPL, pp. 181-193 Schleiffer, C. (2006). Design of Host Interface for COPACOBANA.

Technical report, Studienarbeit, Host Gortz Institute, Ruhr University Bochum Appendices Figure 1-Electronic Codebook (ECB) Mode Figure 2-Cipher Block Chaining (CBC) Mode Table 1: DES Mode Summary Type Initialization Vector Errors Propagate ECB Block None No CBC Block Yes Yes CFB Stream Yes Yes OFB Stream Yes No CTR Stream Counter No.

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