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Implementation of Risc Processor in Fpga Using Verilog Essay

Reduced instruction-set computers (RISC) are designed to have a small set of instructions that execute in short clock cycles, with a small number of cycles per instruction. RISC machines are optimized to achieve efficient pipelining of their instruction streams. The machine also serves as a starting point for developing architectural variants and a more robust instruction set

Designers make high-level tradeoffs in selecting an architecture that serves an application. Once architecture has been selected, a circuit that has sufficient performance (speed) must be synthesized. Hardware description languages (HDLs) play a key role in this process by modeling the system and serving as a descriptive medium that can be used by a synthesis tool.

2. RISC (Reduced Instruction Set Computer)

The nature of RISC architecture and semiconductors rapid technical improvements, RISC embedded platforms have become the best choice for embedded applications.

RISC performance characteristics:

Power Critical

Battery powered and typically less than 2 Watts of power consumption for a whole SBC using an ARM processor, compared to around 15+ Watts for a x86-based SBC.

Space Critical

With a low power solution, the main system can fit into very compact space, eliminating heat dissipation concerns.

Environmental Critical

Because of the lack of heat generation, the RISC system can be fully enclosed for total protection from the environment

Cost Critical

RISC embedded solutions usually come with application-oriented processors that provide a lower cost of ownership because of faster time to market, less development risk and greater overall added value.

Typical RISC applications:

• Industrial mobile platforms

• Touch based Human Machine Interface (HMI)

• Point of information (POI) or Point of Scales (POS)

• In vehicle – Telemetric

• Data collector

• Security controller

2.1 STEPS INVOLVED IN THE PROJECT

3.

3. Architecture of RISC Stored Program Machine

[pic]

The machine consists of three functional units:

• Processor

• Controller

• Memory

Program instructions and data are stored in memory. In program-directed operation, instructions are fetched synchronously from memory, decoded, and executed to

➢ operate on data within the arithmetic and logic unit (ALU)

➢ change the contents of storage registers

➢ change the contents of the program counter (PC), instruction register (IR) and the address register (ADD_R)

➢ change the contents of memory,

➢ Retrieve data and instructions from memory control the movement of data on the system busses.

The instruction register contains the instruction that is currently being executed. The program counter contains the address of the next instruction to be executed and the address register holds the address of the memory location that will be addressed next by a read or write operation

3.1 RISC_SPM: Processor

The processor includes registers, datapaths, control lines, and an ALU capable of performing arithmetic and logic operations on its operands, subject to the opcode held in the instruction register. A multiplexer Mux_l, determines the source of data for Bus_l, and a second mux, Mux_2, determines the source of data for Bus_2. The input datapaths to Mux_l are from four internal general-purpose registers (RO, Rl, R2, R3), and from the Pc. The
contents of Bus_l can be steered to the ALU, to memory, or to Bus_2 (via Mux_2). The input datapaths to Mux_2 are from the ALU, Mux_l, and the memory unit. Thus, an instruction can be fetched from memory, placed on Bus_2, and loaded into the instruction register. A word of data can be fetched from memory, and steered to a general-purpose register or to the operand register (Reg_Y) prior to an operation of the ALU. The result of an ALU operation can be placed on Bus_2, loaded into a register, and subsequently transferred to memory. A dedicated register (Reg_Z) holds a flag indicating that the result of an ALU operation is 0.

3.2 RISC_SPM: Controller

The timing of all activity is determined by the controller. The controller must steer data to the proper destination, according to the instruction being executed. Thus, the design of the controller is strongly dependent on the specification of the machine’s ALU and datapath resources and the clocking scheme available. Here a single clock is used, and execution of an instruction is initiated on a single edge of the clock (the rising edge). The controller monitors the state of the processing unit and the instruction to be executed and determines the value of the control signals. The controller’s input signals are the instruction word and the zero flag from the ALU. The signals produced by the controller are identified as follows:

[pic]

Thus the control unit

➢ determines when to load registers

➢ selects the path of data through the multiplexers

➢ determines when data should be written to memory

➢ Controls the three-state busses in the architecture.

RISC SPM: Instruction Set
The machine is controlled by a machine language program consisting of a set of instructions stored in memory. So, in addition to depending on the machine’s architecture, the design depends on the processor instruction set (i.e., the instructions that can be executed by a program). A machine language program consists of a stored sequence of 8-bit words (bytes). The format of an instruction of RISC_SPM can be long or short depending upon the operation.

Short instructions have the format
| opcode | source | destination | | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 |

Each shot instruction requires one byte of memory. The word has a 4-bit opcode, a 2-bit source register address, and a 2-bit destination register address.
Long instructions have the format
| opcode | source | destination | | 0 | 1 | 1 | 0 | 1 | 0 | Don’t |Don’t | | | | | | | |cares |cares | | address | | 0 | 0 | 0 | 1 | 1 | 1` | 0 | 1 |

A long instruction requires 2 bytes of memory. The first word of a long instruction contains a 4-bit opcode. The remaining 4 bits of the word can be used to specify the address of a pair of source and destination registers, depending on the instruction. The second word contains the address of the memory word that holds an operand required by the instruction. The
instruction mnemonics and their actions are limited below.

Single-Byte Instructions
• NOP: Here no operation is performed; all registers retain their values. The address of the source and destination registers is dint care’s, they have no effect. • ADD: Adds the contents of the source and destination registers and stores the result into destination register. • AND: Forms the bitwise-and of the contents of the source and destination registers and stores the result into the destination registers. • NOT: Forms the bitwise-and of the contents of the source register and stores the result into the destination register. • SUB: Subtracts the contents of the source register from destination register and stores the result into source register. Two-Byte Instructions

• RD: Fetches a memory word from the location specified by the second byte and loads the result into the destination register. The source register bits are don’t cares which means that they are unused. • WR: Writes the contents of the source register to the word in memory specified by the address held in the second byte. The destination register bits are don’t cares which means that they are unused. • BR: Branches the activity flow by loading the program counter with the word at the location (address) specified by the second byte of the instruction. The source register bits and the destination register bits are don’t cares which means that they are unused. • BRZ: Branches the activity flow by loading the program counter with the word at the location (address) specified by the second byte of the instruction if zero flag register is asserted. The source register bits and the destination register bits are don’t cares which means that they are unused.

Instruction set of RISC_SPM machine

| Instruction | Instruction Word | Action | | | Opcode | Source | Destination | | | NOP | 0000 | ?? |
?? | None | | ADD | 0001 | src | dest | dest


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